Vedic Mathematics Based Multiply Accumulate Unit

This paper illustrates the implementation of Multiply-Accumulate unit (MAC) to improve performance using the Ancient Indian Vedic Mathematics. Real-time signal processing needs high speed and high yield Multiplier-Accumulator (MAC) unit that consumes less power, which is always a key to achieve a high performance digital signal processing system. Speed of the multiplier is essential to MAC unit. Vedic Mathematics is the ancient mathematics. There are sixteenth unique sutras in the Vedic mathematics. The Sutras saves effort and time required in solving the problems as compared to the formal methods. The Sutra “Urdhav Triyagbhyam” (Vertical and Crosswise) is used inside the MAC unit as a multiplier. The coding is done in VHDL, synthesis is done in Xilinx ISE series and the FPGA synthesis is done using Xilinx Spartan library. The results show that design of MAC unit using Vedic multiplication is much more efficient in terms of delay and speed compared to conventional multiplication.

This paper describes a 16-b fixed point digital signal processor (DSP), especially its multiply-accumulate (MAC) unit, memories, and instruction set. By adopting a redundant binary multiplier and a variable pipeline structure, this DSP's MAC unit, compared to a conventional MAC unit, consumes about 15% less power and operates 24% faster. Furthermore, its double-speed MAC mechanism can realize twice the performance of a single MAC operation while consuming only 69% more power. By being able to more finely control which portions of memory are activated, the data ROM and data RAM's precharge current was reduced to about 1/8 of the conventional ROM and RAMs. We redesigned the instruction set and reduced its width from 32 b to 24 b based on the analysis of data generated by simulating an application program on our previous DSP. The reduction in instruction width made our on-chip instruction memory size 33% smaller than the previous one. This chip is fabricated with a 0.5-/spl mu/m double-metal-layer CMOS process and achieves 80-MOPS-peak double speed multiply-accumulate performance.

In this work, carry-free redundant arithmetic based fused multiply-accumulate (MAC) units are designed. In the first design, a regular redundant carry-save MAC unit is designed using well known carry-save techniques. In the second design, a hybrid design is proposed to exploit fast carry chains of the FPGA together with double carry-save output encoding. The proposed scheme exploits fast-carry chains of the FPGA structure, and, multi-operand adders are divided into smaller blocks to increase the performance. The outputs of the multi-operand adders are not merged and the results are kept in double carry-save format where extra redundancy reduces critical path delay. Designed MAC units have 16×16-bit multiplier with 40-digit accumulate output for recursive multiply-add operations. The designs are synthesized on Altera <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> Stratix III FPGAs and provide superior performance compared to conventional pipelined carry-propagate multiply-accumulate units. The fusion in the arithmetic structure provides best performance compared to conventional pipelined multiplier based structures, hard multiplier based MAC units, and carry free redundant arithmetic based MAC structures as well.

In this article, we demonstrated a high-throughput gate-level-pipelined 8-bit multiply-accumulate (MAC) unit with a long feedback loop using low-voltage rapid single-flux quantum (LV-RSFQ) logic. The long feedback loop in the MAC unit is an obstacle for high-throughput operation because the logic gates must wait for the delayed inputs from the feedback loop. The LV-RSFQ logic makes high-frequency operation even more difficult by larger and more variable feedback delay. We design the feedback loop by using counter-flow clocking and adding many D flip-flops to divide the long feedback loop into shorter paths. The target clock frequency of the MAC unit with a feedback loop was set to 30 GHz by the experimental results of the MAC unit without a feedback loop. We model the clock frequency and its circuit overhead in a feedback loop to design the feedback loop in the MAC unit achieving 30 GHz with a minimum overhead. The test chips are fabricated using the national institute of advanced industrial science and technology (AIST) 10-kA/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{^{2}}$</tex-math></inline-formula> Advanced Process 2. We have successfully obtained high-throughput 30-GHz operations in the LV-RSFQ MAC unit with a long feedback loop by using the model-based design. The maximum operating frequency of the MAC unit reaches 40 GHz.

Wireless Sensor Network (WSN) presents significant challenges for the application of distributed signal processing and distributed control. These systems will challenge us to apply appropriate techniques to construct capable processing units with sensing nodes considering energy constraints. Digital Signal Processing (DSP) is one of the capable processing units, but it is not commonly used in WSN because of the power constraint. The Multiply-Accumulate Unit (MAC) is the main computational kernel in DSP architectures. The MAC unit determines the power and the speed of the overall system; it always lies in the critical path. Developing high speed and low power MAC is crucial to use DSP in the future WSN. In this work, a fast and low power MAC Unit is proposed. The proposed architecture is based on examination of the critical delays and hardware complexities of merged MAC architectures to design a unit with a low critical path delay and low hardware complexity. The new architecture reduces the hardware complexity of the summation network, thus reduces the overall power. Increasing the speed of operation is achieved by feeding the bits of the accumulated operand into the summation tree before the final adder instead of going through the entire summation network. The ASIC implementation of the proposed 32-bit MAC unit saves 5.5% of the area, 9% of the energy, and reduces the delay by 13% compared to the regular merged MAC unit.

We propose a high-speed and energy-efficient two-cycle multiply-accumulate (MAC) architecture that supports two's complement numbers, and includes accumulation guard bits and saturation circuitry. The first MAC pipeline stage contains only partial-product generation circuitry and a reduction tree, while the second stage, thanks to a special sign-extension solution, implements all other functionality. Place-and-route evaluations using a 65-nm 1.1-V cell library show that the proposed architecture offers a 31% improvement in speed and a 32% reduction in energy per operation, averaged across operand sizes of 16, 32, 48, and 64 bits, over a reference two-cycle MAC architecture that employs a multiplier in the first stage and an accumulator in the second. When operating the proposed architecture at the lower frequency of the reference architecture the available timing slack can be used to downsize gates, resulting in a 52% reduction in energy compared to the reference. We extend the new architecture to create a versatile double-throughput MAC (DTMAC) unit that efficiently performs either multiply-accumulate or multiply operations for N-bit, 1 × N/2-bit, or 2 × N/2-bit operands. In comparison to a fixed-function 32-bit MAC unit, 16-bit multiply-accumulate operations can be executed with 67% higher energy efficiency on a 32-bit DTMAC unit. © 2006 IEEE.

Multipliers act as processors and take on the notable work of many computing frameworks. The speed of the processor is profoundly affected by the speed of their multipliers. In order to improve the system speed, faster and more efficient multipliers should be used. A Vedic multiplier is one of the best solution that can be used to perform multiplications at a faster rate by eliminating the steps that are not needed in usual multiplication process. Power consumption is another critical issue in embedded systems that cannot be ignored. Reversible logic has become notable in the recent years because of its potential to reduce power utilization, which is a major concern in digital design. In this work, a high-speed 16 × 16 Vedic multiplier was designed using Urdhva Tiryagbhyam (UT) sutra, which is derived from Vedic mathematics. This is a simple structure as well as an unbeatable combination for creating any complex multiplication operations for services where speed is of prime importance. This work also proposes a new method based on Elliptic Curve Cryptography (ECC) system for encryption and decryption using Vedic multiplication. By using Vedic Multiplication in ECC the processing time is perfectly reduced. The proposed Elliptic curve cryptography method is much faster than other elliptic curve cryptographic algorithms. Compared to other cryptographic techniques, the key size required to provide equivalent security is small in ECC.

Wearable real-time Electrocardiogram (ECG) monitoring is an emerging wireless technology enabling early diagnosis and increased ability of prevention of cardiovascular diseases. However, the ECG signal suffers from Powerline Interference (PLI) which corrupts the biomedical recordings. Low power and high speed filtering of the ECG signal is essential to make the monitoring device portable. This paper proposes an FIR (Finite Impulse Response) filter based on Multiply-Accumulator (MAC) Unit to suppress the PLI noise. The performance of this filter largely depends on the speed and power of the MAC unit employed inside the filter. The current work compares various MAC units on Power, Performance and Area (PPA) benchmarks. It is shown that Booth-Wallace-Carry Look Ahead adder(CLA) based MAC is optimised for both timing and power which shows 6.2% improvement in performance and 12.1% reduction in power from other implemented designs. Thus, the real-time low power FIR filter is realised using Booth-Wallace-CLA MAC. The convergence time of the algorithm is observed to be less than 0.2 μsec with significant power savings to improve battery life.

The Vedic multiplier is derived from the ancient mathematics called Vedic mathematics .The ancient mathematics has different sutras in that we use Urdhva Tiryagbhyam sutra which means clock wise and vertically . As we know that binary multiplication is not possible so that instead we use binary addition or subtraction instead of it. The key process for the multiplication is the speed of the processor. The fastest mode of multiplication is the Vedic multiplier. In this paper we want to show the delay and utilization of components available for the multiplier by executing the code. The comparison of delay from some papers was also proposed in this paper. The research is going on the Vedic mathematics to overcome the problems on the conventional mathematics. In future Vedic multiplier plays an important role in the DSP (Digital Signal Processing).As it is the fastest and efficient mode of operation. In this paper I am calculating the bit wise delay up to 32-bit. The whole analysis was done in Xilinx. The ISM wave forms for every bit up to 32-bit was to be obtained. The utilization, used, available, utilized analysis was also taken. The whole process was done in XILINX software.

Quantum dot cellular automata (QCA) is a hopeful technology in the field of nanotechnology that seems to suite well with signal‐processing needs. It is concerned with great interest because of its benefits such as ultra‐low power consumption, small size and can operate at one Terahertz. The multiply accumulator (MAC) unit is considered as one of the essential operations in digital signal processing (DSP). In the real‐time DSP systems, several applications like speech processing, video coding, and digital filtering etc. require MAC operations. However, the power dissipation and area are the most significant aspects in these systems. Here, the authors design low power MAC unit based on QCA technology. QCADesigner version 2.0.3 is used to validate the accuracy of the proposed circuit. The reliability of this unit is taken at different temperatures. The power dissipation is estimated using QCAPro tool. The total power consumed by this unit is 2.183 μW. The proposed circuit has 90% improvement in terms of power over complementary metal–oxide–semiconductor (CMOS) circuits. Since the works in the field of QCA logic signal processing has started to progress, the suggested contribution will give rise to a new thread of research in the field of real‐time signal and image treatment.

All computing units, including the Digital Signal Processing (DSP) applications, Multiply Accumulate Unit (MAU), and Arithmetic Logic Unit (ALU), require high speed multipliers. The efficiency of data multiplication is a common performance limiter for DSP systems. Therefore, there is a great need right now for multiplier algorithms that are fast and consume less energy. The design of fast and speed efficient multipliers based on symmetric stacking-based binary counters. This study analyses a Wallace tree multiplier using symmetric stacking-based counters as well as traditional counters. In terms of latency and area, the performance is also contrasted. Verilog HDL and Xilinx are used in programming and synthesis.

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).

Vedic mathematics is a relatively recent subject of study that requires integration with other areas of study. It is a collection of formulas taken from ancient Vedic scriptures. Here, we have combined Vedic mathematics with computer science. Specifically, we have created C++ programmes utilising two Vedic mathematics sutras: URDHVA TIRYAGBHYAM (Sutra-3) SQUARE BY DUPLEX (4-DIGITS). These two techniques speed up computations compared to more conventional techniques. We can discover the product and square of huge numbers with ease and with fewer errors when we use these two sutras.

Design and Implementation of 64 Bit IIR Filters Using Vedic Multipliers

This paper describes the new Fairchild family of integrated circuits which will allow the development of high performance digital signal processing systems with a small number of building block circuits.