ENHANCING ARITHMETIC OPERATIONS IN C++ THROUGH VEDIC MATHEMATICS PRINCIPLES

In most of the digital signal processing (DSP) applications the critical operations are the multiplication and accumulation. Real-time signal processing requires high speed and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which is always a key to achieve a high performance digital signal processing system. In this paper, design of MAC unit is proposed. The multiplier used inside the MAC unit is based on the Sutra "Urdhva Tiryagbhyam" (Vertically and Cross wise) which is one of the Sutras of Vedic mathematics. Vedic mathematics is mainly based on sixteen Sutras and was rediscovered in early twentieth century. In ancient India, this Sutra was traditionally used for decimal number multiplications within less time. The same concept is applied for multiplication of binary numbers to make it useful in the digital hardware. Here, the coding is done in VHDL and synthesis is done in Xilinx ISE series. The combinational delay obtained after synthesis is compared with the performance of the "Modified Booth Wallace Multiplier" and "High speed Vedic multiplier" presented by Ramesh Pushpangadam. Our proposed Vedic multiplier seems to have better performance.

Multipliers act as processors and take on the notable work of many computing frameworks. The speed of the processor is profoundly affected by the speed of their multipliers. In order to improve the system speed, faster and more efficient multipliers should be used. A Vedic multiplier is one of the best solution that can be used to perform multiplications at a faster rate by eliminating the steps that are not needed in usual multiplication process. Power consumption is another critical issue in embedded systems that cannot be ignored. Reversible logic has become notable in the recent years because of its potential to reduce power utilization, which is a major concern in digital design. In this work, a high-speed 16 × 16 Vedic multiplier was designed using Urdhva Tiryagbhyam (UT) sutra, which is derived from Vedic mathematics. This is a simple structure as well as an unbeatable combination for creating any complex multiplication operations for services where speed is of prime importance. This work also proposes a new method based on Elliptic Curve Cryptography (ECC) system for encryption and decryption using Vedic multiplication. By using Vedic Multiplication in ECC the processing time is perfectly reduced. The proposed Elliptic curve cryptography method is much faster than other elliptic curve cryptographic algorithms. Compared to other cryptographic techniques, the key size required to provide equivalent security is small in ECC.

The Vedic multiplier is derived from the ancient mathematics called Vedic mathematics .The ancient mathematics has different sutras in that we use Urdhva Tiryagbhyam sutra which means clock wise and vertically . As we know that binary multiplication is not possible so that instead we use binary addition or subtraction instead of it. The key process for the multiplication is the speed of the processor. The fastest mode of multiplication is the Vedic multiplier. In this paper we want to show the delay and utilization of components available for the multiplier by executing the code. The comparison of delay from some papers was also proposed in this paper. The research is going on the Vedic mathematics to overcome the problems on the conventional mathematics. In future Vedic multiplier plays an important role in the DSP (Digital Signal Processing).As it is the fastest and efficient mode of operation. In this paper I am calculating the bit wise delay up to 32-bit. The whole analysis was done in Xilinx. The ISM wave forms for every bit up to 32-bit was to be obtained. The utilization, used, available, utilized analysis was also taken. The whole process was done in XILINX software.

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).

Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

Training of operations research of bachelors of Computer Science is particularly important because combines both fundamental concepts and principles of mathematics and informational different disciplines and applied models and algorithms for their use. One of the urgent problems of higher education is creation of a methodological training systems targeted at a broad, yet educationally balanced use of modern learning process and information and communication technologies, including computer systems of mathematics. It is scientifically based, educationally balanced and appropriate implementation of these tools in the educational institutions will increase the level of information technological support and substantial growth of informational and fundamental mathematical training of future specialists in computer science. Because of this, there is need to identify ways of using ICT in learning process of operations research of Bachelor of Computer Science in Pedagogical Universities, modernizing the learning environment, taking into account trends in the development of science and technology, improving teaching training systems, including through the use of computer mathematics system as learning tools. This article analyzes the experimental study of effectiveness of using the system Maxima methods in learning of operations research of bachelors of computer science. The article outlines the pedagogical directions of use of computer mathematics system (CMS) at studying operations research; highlights the methodological aspects of CMS Maxima in the study of this course. The purpose of the article is an experimental trial of CMS Maxima as a means of teaching of operations research of bachelors of computer science. The object of investigation is the learning process of bachelors of computer science with the use of CMS. The subject of investigation is the peculiarities of CMS Maxima using as a learning tool of support for computer science courses.

Modern software systems increasingly rely on numerical algorithms that require high or arbitrary precision, especially in scientific computing, numerical modeling, optimization, and data analysis. The use of high-precision arithmetic significantly affects the computational behavior of programs, since the cost of arithmetic and transcendental operations depends on the precision level of numerical data representation. In such conditions, predicting program execution time and estimating computational complexity become non-trivial tasks, particularly in distributed computing environments. This paper presents an analysis of existing software complexity metrics with respect to their applicability to programs performing high-precision computations in distributed systems. Classical software metrics, including size metrics, control flow complexity metrics, and data flow complexity metrics, are considered and systematized. Their main limitations are identified in the context of high-precision arithmetic, where the assumption of constant-time arithmetic operations is no longer valid. It is shown that classical complexity metrics do not account for the dependence of computational cost on the mantissa length of numerical variables and the actual cost of arithmetic operations. As a result, programs with relatively simple control structures but intensive high-precision computations may require significantly more computational resources than programs with complex control logic implemented using standard floating-point arithmetic. The study substantiates the necessity of extending existing complexity evaluation approaches by incorporating parameters related to numerical precision and operation cost. The computational complexity of a program is proposed to be considered as a function of the types of arithmetic operations, their execution frequency, and the mantissa length of numerical data. Such an approach allows for a more accurate estimation of execution time and resource consumption, which is especially important for programs executed in distributed computing systems where communication overhead and data transfer costs play a significant role. The obtained results can be used for preliminary performance estimation, rational resource allocation, and the selection of appropriate parallelization strategies for high-precision numerical software in distributed environments.

Work in Progress—In-depth coverage of arithmetic operations in an introductory digital logic course equips students with the background knowledge necessary for high-level Computer and Electrical engineering and Computer Science courses. In this paper, we propose a new method of teaching digital logic based on including a module on fixed-point and floating-point arithmetic operations during the first four weeks of the course, and then theming the whole course around this module without sacrificing the recommended course outcomes. The paper shows that theming the whole course around arithmetic operations helps students to achieve the course outcomes, makes the course interesting, ties the course to real-life applications, and teaches students how to implement and compare alternative designs.

A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

This paper presents a high-speed Vedic multiplier based on the Urdhva Tiryagbhyam sutra of Vedic mathematics that incorporates a novel adder based on Quaternary Signed digit number system. Three operations are inherent in multiplication: partial products generation, partial products reduction and addition. A fast adder architecture therefore greatly enhances the speed of the overall process. A Quaternary logic adder architecture is proposed that works on a hybrid of binary and quaternary number systems. A given binary string is first divided into quaternary digits of 2 bits each followed by parallel addition reducing the carry propagation delay. The design doesn't require a radix conversion module as the sum is directly generated in binary using the novel concept of an adjusting bit. The proposed multiplier design is compared with a Vedic multiplier based on multi voltage or multi value logic [MVL], Vedic Multiplier that incorporates a QSD adder with a conversion module for quaternary to binary conversion, Vedic multiplier that uses Carry Select Adder and a commonly used fast multiplication mechanism such as Booth multiplier. All these designs have been developed using Verilog HDL and synthesized by Synopsys Design Compiler. They have been realized using the open source NAN gate 15nm technology library. The proposal shows a maximum of 88.75% speed improvement with respect to Multi Value logic based 128x128 Vedic multiplier while the minimum is 17.47%.

The adapted modular number system (AMNS) is an integer number system which aims to speed up arithmetic operations modulo a prime p. Such a system is defined by a tuple $$(p, n, \gamma , \rho , E)$$, where p, n, $$\gamma $$ and $$\rho $$ are integers and $$E\in \mathbb {Z}[X]$$. In El Mrabet and Gama (in: WAIFI, lecture notes in computer science, Springer, 2012) conditions required to build AMNS with $$E(X)=X^n + 1$$ are provided. In this paper, we generalise their approach and provide a method to generate multiple AMNS for a given prime p with $$E(X)=X^n-\lambda $$ and $$\lambda \in \mathbb {Z}{\setminus }\{0\}$$. Moreover, we propose a complete set of algorithms without conditional branching to perform arithmetic and conversion operations in the AMNS, using a Montgomery-like method described in Negre and Plantard (in: Information security and privacy, 13th Australasian conference, ACISP 2008, Wollongong, Australia, 2008). We show that our implementation outperforms GNU MP and OpenSSL libraries. Finally, we highlight some properties of the AMNS which state that it could lead to a helpful countermeasure against some side-channel attacks.

Modern GPUs are widely used for diverse applications, particularly data-parallel tasks like machine learning and scientific computing. However, their efficiency is hindered by architectural limitations, inherited from historical RISC processors, in handling memory loads causing high register file contention. We observe that a significant number (around 26%) of values present in the register file are typically used only once, contributing to more than 25% of the total register file bank conflicts, on average. This paper addresses the challenge of single-use memory values in the GPU register file (i.e. data values used only once) which wastes space and increases latency. To this end, we introduce a novel mechanism inspired by CISC architectures. It replaces single-use loads with direct memory operands in arithmetic operations. Our approach improves performance by 20% and reduces energy consumption by 18%, on average, with negligible (<1%) hardware overhead.

Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing systems allows one to implement MPA algorithms in hardware. Whereas addition and subtraction operations of two n-digit numbers require O(n) operations, the basecase multiplication is equivalent to the convolution computation that requires O(n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) operations. Therefore, an efficient implementation of the multiplication operation is crucial for application of the reconfigurable hardware in MPA computations. In this contribution, our implementation of the base case-multiplication algorithm in MPA on FPGA is presented. The method is implemented using the very high speed integrated circuit hardware description language (VHDL) and benchmarked on Xilinx Artix-7 FPGA. In the developed implementation of the MPA multiplication, the multiplication of two integer 1024-bit numbers (2048-bit numbers) takes 205 nsec (819 nsec) with the use of 40 DSP modules. It gives two-fold speedup in comparison to the reference results published in the literature. The developed digital circuit of the MPA multiplier works with integer numbers of precision varying in the range between 16 bits and 32 kbits. Such a scalability allows one to use the developed method not only in scientific computing, but also in embedded systems employing encryption based on MPA.

A number system uses a set of digits and sign to represent all the numbers. Different number systems use different amount of digits and sign. To compare the leanness of a number system, the cardinality of the complete set of digits and sign are employed in this work. The 01 binary number system is used by almost all the modern computers. It can represent all the real numbers by two digits 0, 1 and a sign (-), which means its cardinality is 3. Thus, the 01 binary system is not a true binary system. After reviewing all the existing number systems it is found that no true binary system exists for real numbers. All the current binary number systems either don’t have radix 2, or have cardinality 3. In this paper, a true binary system for real numbers, with both radix and cardinality 2, is invented based on the principle of Yin-Yang. Surprisingly, this binary system can not only represent all real numbers without using a sign, but also perform arithmetic and Boolean operations without any problem. Furthermore, due to its radix being 2, this true binary system is compatible with the 01 binary system and many operations are interchangeable between the two systems. It is expected that this true binary system will be applied in the fields of number representation, computer science and cryptography.

Floating-point arithmetic is ever-present in computer systems. All most all computer languages has supports a floating-point number types. Most of the computer compilers called upon floating-point algorithms from time to time for execution of the floating-point arithmetic operations and every operating system must be react virtually for floating-point exceptions like underflow and overflow. The double-precision floating arithmetic is mainly used in the digital signal processing (filters, FFTs) applications, numerical applications and scientic applications. The double-precision floating arithmetic operations are the addition, the subtraction, the multiplication, and the division. Among the all arithmetic operations, multiplication is widely used and most complex arithmetic operation. The double-precision (64-bit) floating point number is divide into three fields, Sign field, Exponent field and Mantissa field. The most significant bit of the number is a sign field and it is a 1-bit length, next 11-bits represents the exponent field of the number and remaining 52-bits are represents the mantissa field of the number. The double-precision floating-point multiplier requires a large 52×52 mantissa multiplications. The performance of the double-precision floating number multiplication mainly depends on the area and speed. The proposed work presents a novel approach to decrease this huge multiplication of mantissa. The Urdhva Tiryagbhyam technique permits to using a smaller number of multiplication hardware compared to the conventional method. In traditional method adding of the partial products are separately done and it takes more time in comparison with the proposed method. In proposed method the partial products are concurrently added with the multiplication operaton and it can reduce the time delay. The double-precision floating multiplier is implemented using Verilog HDL with Xilinx ISE tools on Virtex-5 FPGA.