10/24 GHz CMOS/GIPD單脈衝式接收機設計

Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'.<br/><br/>In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. <br/><br/>Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended.<br/><br/>In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. <br/><br/>We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. <br/><br/>One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.

MuCCRA-3 is a low power coarse-grained Dynamically Reconfigurable Processor Array (DRPA) for a flexible off-loading engine in various SoC (System-on-a-Chip). Similar to the other DRPAs, it has an array of processing elements (PEs), a simple coarse-grained processor, consisting of an ALU and a register file, and dynamic reconfiguration of the array enables time-multiplexed execution. DRPAs including MuCCRA-3 provide multiple sets of configuration data called hardware contexts, and switch them in a clock cycle. For low power computation, the PE array structure of MuCCRA-3 is optimized according to the evaluation results of previous prototypes, MuCCRA-1 and 2[1], and was implemented with 65nm low power CMOS process from Fujitsu. By using a real chip, the power consumption and performance are evaluated. The evaluation results suggest that MuCCRA-3 works with extremely low power: 10mW–13mW.

The objective of this paper is to compare the power consumption, leakage voltage, leakage current and leakage power of 3-T DRAM while maintaining the competitive performance .The MTCOS and SVL technique is used in 3T DRAM to compare the performance. Multi-threshold CMOS(MTCMOS) is a CMOS chip which has a Transistor with multiple threshold voltage and SVL is a technique which used to reduce leakage during both the active and stand-by mode. DRAM was first invented by Dr. Robert Dennard in the year 1966. It is used in many advanced processor for chip instruction and data memory. It majorly contributes in power dissipation in off-state leakage current. In personal computers it is used as the main memory, workstations etc. The basic advantage of using DRAM is its simplicity in its structure. Keyword- DRAM; FinFET; CMOS; Leakage power; Leakage current; Frequency; Access time; MTCMOS; SVL; USVL; LSVL

A self-sustained multi-sensor platform for indoor environmental monitoring is proposed in this paper. To reduce the cost and power consumption of the sensing platform, in the developed platform, organic materials of PEDOT:PSS and PEDOT:PSS/EB-PANI are used as the sensing films for humidity and CO2 detection, respectively. Different from traditional gas sensors, these organic sensing films can operate at room temperature without heating processes or infrared transceivers so that the power consumption of the developed humidity and the CO2 sensors can be as low as 10 μW and 5 μW, respectively. To cooperate with these low-power sensors, a Complementary Metal-Oxide-Semiconductor (CMOS) system-on-chip (SoC) is designed to amplify and to read out multiple sensor signals with low power consumption. The developed SoC includes an analog-front-end interface circuit (AFE), an analog-to-digital convertor (ADC), a digital controller and a power management unit (PMU). Scheduled by the digital controller, the sensing circuits are power gated with a small duty-cycle to reduce the average power consumption to 3.2 μW. The designed PMU converts the power scavenged from a dye sensitized solar cell (DSSC) module into required supply voltages for SoC circuits operation under typical indoor illuminance conditions. To our knowledge, this is the first multiple environmental parameters (Temperature/CO2/Humidity) sensing platform that demonstrates a true self-powering functionality for long-term operations.

A double-edge-triggered digital low dropout regulator (DLDO) is proposed with a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) for a system-on-chip (SoC) application. To achieve a fast transient response, the main comparator generates the comparison result at the rising edge of the AVC, and this result is sampled by the coarse or fine bidirectional shifter register at the falling edge of the AVC. Furthermore, the clock frequency can be boosted from 8 MHz at the steady state to 50 MHz by the AVC when the output current suffers from a sudden change, and it can also be adjusted in real-time according to the output voltage, which avoids the oscillation phenomenon and decreases the power consumption during the recovery process. To further lower the power consumption, the self-clock comparator replaces the conventional static comparator in the transient detector. The post-simulation results show that the proposed DLDO consumes a quiescent current of 95.13 μA in the steady state, and drives a maximum load current of 25 mA at the supply power of 0.6 V with an active area of 0.053-mm2 in a 180 nm CMOS process. When the load current jumps from 0.5 mA to 25 mA at the edge of 100 ps, the undershoot voltage and overshoot voltage are only 335 mV with the recovery time of 2.7 μs and 47.6 mV with the recovery time of 2.1 μs at the total on-chip capacitor of 50 pF, respectively, resulting in two competitive figures of merits (FoMs) than the previous works.

Flexible and wearable devices are emerging with the developing of the sensors and IoT (internet of the things). The power consumption and volume of such devices are dominant limitations for wearable feature in various applications. To meet the requirements, a photoacoustic receiver system-on-chip (SoC) is developed and fabricated with a novel correlation detection technique based on the early-and-late tracking. Through this method, output SNR of the receiver can be significantly improved. For this, a low power and high sensitivity analog front-end (AFE) with a noise shaping (NS) SAR ADC is implemented. As oversampling is necessary for the accurate delay of digital processing, noise shaping technique is implemented in the SAR ADC. Simulation results show that, the AFE achieves 70 dB dynamic range and 20 μV sensitivity for about 30 dB output SNR. The SAR ADC can obtain 71 dB SNDR under 50MSps sampling rate with the aid of the NS technique. Based on the analog circuits design, the digital part for the detecting technique is also implemented on chip. The whole power consumption is about 15 mW on the TSMC 65 nm CMOS process.

Efficient design and optimization of flip-flops can significantly affect overall circuit performance as they have many applications in digital systems which can impact the overall power consumption and timings of the emerging system on chips (SOCs). In this paper, modeling, design, and optimization of transmission gate-based master-slave positive-edge-triggered flip-flop (TGFF) in 16 nm complementary metal-oxide semiconductor (CMOS) is proposed. The proposed deep neural network (DNN)-based optimization method first generates an accurate model for different performance metrics by using the training data obtained from transistor-level models which are over 100 times faster than them. Then, these accurate DNN-based models are used to optimize design goals such as dynamic and static power, setup time, and propagation delay (Data to Output). Using these fast, accurate models significantly speed up the design procedure and leads to a considerably more optimized design. Additionally, as the DNN is a universal approximator that can catch any nonlinear input-output relationship, the proposed method can be used to optimize circuits for any performance metric, even if no analytical formula is available. Additionally, circuit design based on the proposed method is automated which, facilitates the tasks of circuit designers.

Designing ideal analogue circuits has become difficult due to extremely large-scale integration. The complementary metal oxide semiconductor (CMOS) analog integrated circuits (IC) could use an evolutionary method to figure out the size of each device. The CMOS operational transconductance amplifier (CMOS OTA) and the CMOS current conveyor second generation (CMOS CCII) are designed using advanced nanometer transistor technology (180 nm). Both CMOS OTA and CMOS CCII have high performance, such as a wide frequency, voltage gain, slew rate, and phase margin, to include very wide applications in signal processing, such as active filters and oscillators. The optimization approach is an iterative procedure that uses an optimization algorithm to change design variables until the optimal solution is identified. In this study, different sorts of algorithms the genetic algorithm (GA), particle swarm optimization (PSO), and cuckoo search (CS) are employed to boost and enhance the performance parameters. While decreasing the time required to develop a conventional operation amplifier's settling time. Some studies decrease the value of the power utilized at various frequencies. Others operate at extremely high frequencies, but their power consumption is greater than that of those operating at lower frequencies.

A CMOS transimpedance amplifier with broad-band and high gain based on negative Miller capacitance

Photoacoustic (PA) imaging and sensing based on optical excitation and acoustic detection are emerging recently. The main issue of the PA systems is the poor SNR at the output of the sensors. The power consumption and size of the receiver are also crucial for the systems. Thus, several techniques are proposed in the analog front-end (AFE) and the analog-to-digital convertor (ADC) to improve the output SNR and power efficiency of the receiver. A resonant noise matching (RNM) technique is proposed to improve the sensitivity of ultrasound transducers. Diverse from the power matching which aims to maximize the output power from transducer in conventional electrical impedance matching (EIM) technique, the RNM maximizes the output voltage. The advantage of RNM is that it can also equivalently reduce the LNA’s input-referred noise and thus minimize the noise figure (NF) of the ultrasound receiver. Measurement results show that, the output signal is improved by 5 times through the proposed RNM technique, which is 66.7% larger than that of conventional methods. In addition, the sensitivity of the receiver is significantly improved by more than 10.4 dB which is beneficial for a variety of applications of piezoelectric ultrasound transducers. Thereafter, a high sensitivity and high dynamic range AFE is developed and fabricated in TSMC 65 nm CMOS process. An LNA with 30 dB gain and low input-referred noise (1 nV/Hz) is designed to amplify the input signal and suppress the noise from subsequent stages. Then a 3rd order Butterworth low-pass filter (LPF) with 5-20 MHz cut-off frequency is connected behind the LNA to reduce the out-of-band noise. Finally, a variable gain amplifier (VGA) which covers a gain range 0-45 dB with 20 MHz bandwidth are implemented in the AFE. The AFE is also applied in a photoacoustic sensor system which can achieve coherent lock-in function to detect weak PA signals noninvasively at in-vivo environments. An asynchronous SAR ADC with a novel mismatch error shaping (MES) technique is designed and fabricated. The power dissipation of the SAR ADC is dominated by the comparator, DAC and digital logic circuits. To reduce digital power consumption, the asynchronous timing sequence is adopted. As known, the resolution of SAR ADC is limited by the non-linearity of DAC and noise of comparator. The linearity of the DAC can be efficiently improved by the MES technique. The proposed novel MES technique can remove the flash ADC and DWA digital circuits in the convention MES technique, and thus improve the power efficiency. Noise shaping technique is also applied in the SAR ADC to reduce the comparator noise and improve the output SNR. In addition, another MES technique based on a double input range SAR ADC is also proposed. Through this method, the input signal is not necessary to be reduced by 2 times, which happens in the first proposed MES. Consequently, the output SNR can be improved by 3 dB. Overall, the main contributions of the thesis are: a) the RNM technique which is designed to improve the sensor’s sensitivity, b) A 0.18µVrms super-sensitivity photoacoustic imager based on coherent detection for deep in-vivo imaging and c) a low power and high-resolution SAR ADC with improved MES technique.

A high speed dual-phase dynamic-pseudo NMOS ((DP)/sup 2/) latch using clocked pseudo-NMOS inverters is presented. Compared to the conventional D-latch, this circuit has a higher maximum operating frequency and consumes lower dynamic power at a given operating frequency. The latch has been demonstrated by utilizing it in the synchronous counter section of a dual-phase dual-modulus prescaler implemented in a 0.8 /spl mu/m CMOS process. The maximum operating frequency for the prescaler at 3 V supply voltage is 1.3 GHz, while the power consumption is 9.7 mW. This power consumption is significantly lower than those of the previously reported prescalers implemented in 0.8 /spl mu/m CMOS processes. The 9.7 mW power consumption at 1.3 GHz also compares favorably to the 24 mW power consumption of the 1.75 GHz prescaler using MOS current mode latches implemented in a 0.7 /spl mu/m CMOS process. A 25% reduction of the maximum operating frequency for a /spl sim/60% reduction of the power consumption should be a useful tradeoff.

We present a new mixed pass-transistor logic (PTL) and static CMOS logic synthesis method based on a genetic search. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/CMOS logic gates using BDDs. The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay or power consumption or both in a 0.25 /spl mu/m CMOS process. The average area, power consumption, and power-delay product of ISCAS85 and MCNC91 benchmark circuits using the proposed method are 25%, 40%, and 45% better than their static counterparts, respectively.

Today, the most common form of mass-production semiconductor device fabrication is Complementary Metal-Oxide Semiconductor (CMOS) technology. The dedicated Integrated Circuit (IC) interfaces of commercial sensors are manufactured using this technology. The sensing elements are generally implemented using Micro-Electro-Mechanical-Systems (MEMS), which need to be manufactured using specialized micro-machining processes. Finally, the CMOS circuitry and the MEMS should ideally be combined in a single package. For some applications, integration of CMOS electronics and MEMS devices on a single chip (CMOS-MEMS) has the potential of reducing fabrication costs, size, parasitics and power consumption, compared to other integration approaches. Remarkably, a CMOS-MEMS device may be built with the back-end-of-line (BEOL) layers of the CMOS process. But, despite its advantages, this particular approach has proven to be very challenging given the current lack of commercial products in the market. The main objective of this Thesis is to prove that a high-performance MEMS, sealed and packaged in a standard package, may be accurately modeled and manufactured using the BEOL layers of a CMOS process in a reliable way. To attain this, the first highly reliable novel CMOS-MEMS Lorentz Force Magnetometer (LFM) was successfully designed, modeled, manufactured, characterized and subjected to several reliability tests, obtaining a comparable or superior performance to the typical solid-state magnetometers used in current smartphones. A novel technique to avoid magnetic offsets, the main drawback of LFMs, was presented and its performance confirmed experimentally. Initially, the issues encountered in the manufacturing process of MEMS using the BEOL layers of the CMOS process were discouraging. Vapor HF release of MEMS structures using the BEOL of CMOS wafers resulted in undesirable damaging effects that may lead to the conclusion that this manufacturing approach is not feasible. However, design techniques and workarounds for dealing with the observed issues were devised, tested and implemented in the design of the LFM presented in this Thesis, showing a clear path to successfully fabricate different MEMS devices using the BEOL. Hoy en día, la forma más común de producción en masa es una tecnología llamada Complementary Metal-Oxide Semiconductor (CMOS). La interfaz de los circuitos integrados (IC) de sensores comerciales se fabrica usando, precisamente, esta tecnología. Actualmente es común que los sensores se implementen usando Sistemas Micro-Electro-Mecánicos (MEMS), que necesitan ser fabricados usando procesos especiales de micro-mecanizado. En un último paso, la circuitería CMOS y el MEMS se combinan en un único elemento, llamado package. En algunas aplicaciones, la integración de la electrónica CMOS y los dispositivos MEMS en un único chip (CMOS-MEMS) alberga el potencial de reducir los costes de fabricación, el tamaño, los parásitos y el consumo, al compararla con otras formas de integración. Resulta notable que un dispositivo CMOS-MEMS pueda ser construido con las capas del back-end-of-line (BEOL) de un proceso CMOS. Pero, a pesar de sus ventajas, este enfoque ha demostrado ser un gran desafío como demuestra la falta de productos comerciales en el mercado. El objetivo principal de esta Tesis es probar que un MEMS de altas prestaciones, sellado y empaquetado en un encapsulado estándar, puede ser correctamente modelado y fabricado de una manera fiable usando las capas del BEOL de un proceso CMOS. Para probar esto mismo, el primer magnetómetro CMOS-MEMS de fuerza de Lorentz (LFM) fue exitosamente diseñado, modelado, fabricado, caracterizado y sometido a varias pruebas de fiabilidad, obteniendo un rendimiento comparable o superior al de los típicos magnetómetros de estado sólido, los cuales son usados en móviles actuales. Cabe destacar que en esta Tesis se presenta una novedosa técnica con la que se evitan offsets magnéticos, el mayor inconveniente de los magnetómetros de fuerza Lorentz. Su efectividad fue confirmada experimentalmente. En los inicios, los problemas asociados al proceso de fabricación de MEMS usando las capas BEOL de obleas CMOS resultaba desalentador. Liberar estructuras MEMS hechas con obleas CMOS con vapor de HF producía efectos no deseados que bien podrían llevar a la conclusión de que este enfoque de fabricación no es viable. Sin embargo, se idearon y probaron técnicas de diseño especiales y soluciones ad-hoc para contrarrestar estos efectos no deseados. Se implementaron en el diseño del magnetómetro de Lorentz presentado en esta Tesis, arrojando excelentes resultados, lo cual despeja el camino hacia la fabricación de diferentes dispositivos MEMS usando las capas BEOL.

Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

Substantial increase in gate and sub-threshold leakage of complementary metal-oxide-semiconductor (CMOS) devices is making it extremely challenging to achieve energy-efficient designs while continuing their scaling at the same pace as in the past few decades. Designers constantly sacrifice higher levels of performance to limit the ever-increasing leakage power consumption. One possible solution to tackle the leakage issue, which is proposed in this work, is to integrate nano-electro-mechanical switches (NEMS) with CMOS technology. Hybrid NEMS-CMOS technology takes advantage of both near-zero-leakage characteristics of NEMS devices along with high ON current of CMOS transistors. The feasibility of integration of NEMS switches into a CMOS process is illustrated by a practical process flow. Moreover, co-design of hybrid NEMS-CMOS as low-power dynamic OR gates, static random access memory (SRAM) cells and sleep transistors is explored. Simulation results indicate that such hybrid dynamic OR gates can achieve 60-80- lower switching power and almost zero-leakage power consumption with minor delay penalty. However, the hybrid OR gate outperforms its CMOS counterpart both in terms of delay and switching power consumption with increase in fan-in beyond 12. Additionally, it is shown that a hybrid NEMS-CMOS SRAM cell can achieve almost 8- lower standby leakage power consumption with only minor noise margin and latency cost. Finally, application of NEMS devices as sleep transistors results in up to three orders of magnitude lower OFF current with negligible performance degradation as compared to CMOS sleep switches.