Performance parameters optimization of CMOS analog signal processing circuits based on smart algorithms

Optimal design of Complementary Metal Oxide Semiconductor (CMOS) differential amplifier circuit using Opposition based Harmony Search technique (OHS) is reported in this work. The original Harmony Search (HS) algorithm is chosen as heart of the OHS for near-global convergence. Each solution in Harmony Memory (HM) is generated on the basis of memory consideration rule, a pitch adjustment rule and a reinitialization process which gives the optimum result corresponding to the least error fitness in multidimensional search space. Incorporation of different control parameters in basic HS algorithm results in balancing of exploration and exploitation of search space. The proposed OHS based CMOS analog amplifier circuit design has alleviated from inherent drawbacks of premature convergence and stagnation, unlike Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Differential Evolution (DE). To confirm the superiority of the OHS based technique, SPICE simulation is also carried out by using the optimized parameters achieved by employing OHS. Results presented for the optimally designed amplifier circuit confirm the superiority of the proposed OHS based technique over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, design criteria and design objectives. Simulation results confirm that OHS based designed amplifier circuit not only provides the least MOS transistor area, but it also provides improved gain and dissipates least power than the reported works.

SummaryThis paper presents the optimal designs of two analogue complementary metal–oxide–semiconductor (CMOS) amplifier circuits, namely differential amplifier with current mirror load and two‐stage operational amplifier. A modified Particle Swarm Optimization (PSO), called Craziness‐based Particle Swarm Optimization (CRPSO) technique is applied to minimize the total MOS area of the designed circuits. CRPSO is a highly modified version of conventional PSO, which adopts a number of random variables and has a better and faster exploration and exploitation capability in the multidimensional search space. Integration of craziness factor in the fundamental velocity term of PSO not only brings diversity in particles but also pledges convergence close to global best solution. The proposed CRPSO‐based circuit optimization technique is reassured to be free from the intrinsic disadvantages of premature convergence and stagnation, unlike Differential Evolution (DE), Harmony Search (HS), Artificial Bee Colony (ABC) and Particle Swarm Optimization (PSO). The simulation results achieved for the two analogue CMOS amplifier circuits establish the efficacy of the proposed CRPSO‐based approach over those of DE, HS, ABC and PSO in terms of convergence haste, design conditions and design goals. The optimally designed analogue CMOS amplifier circuits occupy the least MOS area and show the best performance parameters like gain and power dissipation, in compared with the other reported literature. Copyright © 2016 John Wiley & Sons, Ltd.

This paper presents a monolithic integration of piezoresistive micro-cantilevers with CMOS (complementary metal oxide semiconductor) analog amplifier and digital multiplexer based on the techniques of SOI (silicon on insulator) CMOS and MEMS (micro electronic mechanical system). The three modules, signal detection, signal selection and signal amplification, of the design are proposed step by step. Then, SOI-CMOS-PD (partially depleted) is compared with SOI-CMOS-FD (fully depleted) to ensure its advantages in analog IC. And the post-CMOS process is designed as manufacture solution. Finally, simulations and test results are presented to prove the availability of the whole project.

Optimal design of linear phase multi-band stop filters using improved cuckoo search particle swarm optimization

This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

A two‐stage Class A‐AB operational transconductance amplifier with low power consumption, high slew rate, and high bandwidth is introduced for handling large capacitive loads. Unlike the conventional two‐stage operational transconductance amplifiers that use a Miller capacitor, compensation is provided by the load capacitor (CL) at the output node. The proposed two‐stage amplifier maintains a 45° phase margin (PM) over any load capacitance. This is achieved through a MOSFET‐based RC network at the output node. Dual nMOS/pMOS differential stages drive output directly, improving both SR+ and SR−. Post‐layout simulation results with a capacitive load of 100 pF (CL) demonstrate that the proposed operational transconductance amplifier has a DC gain of 60.1 dB, an excellent average slew rate of 20.3 V/µs, a gain‐bandwidth product of 10.6 MHz, an average 1% settling time of 122.2 ns and a PM of 76.6°, while consuming only 103.5 µW. Reducing the CL to 10 pF reduces the PM to 47.6°, while increasing the gain‐bandwidth and average slew rate to 82.9 MHz and 142.6 V/µs respectively.

A novel meta-heuristic optimization algorithm based MPPT control technique for PV systems under complex partial shading condition

Maximum power point tracking (MPPT) control is one of the essential requirements in harnessing wind power of wind energy conversion systems (WECS). The more precise the maximum power point (MPP) is determined, the more optimal the WECS is operated. Amongst MPPT algorithms, a hill-climb search (HCS) algorithm is preferred because of its simplicity however it also has few drawbacks such as the difficulty of selecting an appropriate step size, the premature convergence phenomenon and the speed-efficiency trade-off. A cuckoo search (CS) algorithm is proposed in this paper for finding out a MPP of a WECS driven by a doubly-fed induction generator (DFIG) under various wind speeds which mostly overcomes the above disadvantages. Then, the DFIG-WECS is controlled to track the MPP. This ensures that the DFIG-WECS is always operated at MPPs regardless of various wind speeds. It is realized that the proposed CS algorithm is also a population-based algorithm inspired from the breeding behavior of cuckoos but it is quite simple, powerful and especially requires less parameters to define optimal solutions than a genetic algorithm (GA) and a particle swarm optimization (PSO) algorithm. Though numerical results, the CS algorithm shows its effectiveness in finding out MPPs in the DFIG-WECS. Furthermore, the obtained results using the CS algorithm are also compared with those using the HCS and PSO algorithms. The comparison demonstrates that the convergence value and speed of the CS algorithm are always better than those of the HCS and PSO algorithms in the MPPT application in the DFIG-WECS.

The cuckoo search (CS) algorithm, which is a new meta-heuristic optimization algorithm, is an efficient approach to solve continuous function optimization problems. Normally, the parameters of the CS are fixed constants. This may result in affecting the algorithm efficiency. To cope with this issue, we properly tune the parameters of the CS and propose an adaptive cuckoo search (ACS) algorithm to enhance the convergence rate and accuracy of the CS. Then, we validate the proposed ACS against test functions and compare its performance with those of particle swarm optimization (PSO), improved cuckoo search algorithm (ICS) and CS by simulation. The simulation results demonstrate that the ACS obtains some solutions better than those obtained by PSO, ICS and CS.

Operational Transconductance Amplifiers (OTAs) are the most pivotal blocks in analog circuits and systems. With the emersion of catastrophic short channel effects for Complementary Metal Oxide Semiconductor (CMOS) transistors at deep nanometric regime, the microelectronics scientists have focused on designing ultra-miniature OTAs based on non-silicon materials. During the last few years, Gate-All-Around Carbon Nanotube Field Effect Transistors (GAA-CNTFETs) with astonishing electrical and physical properties have drawn extensive attention of nanoelectronics researchers as a potential platform to represent high-performance nanoscale OTAs. In this regard, this work aims to propose an ultra-miniature ultra-wideband OTA based on the 10 nm GAA-CNTFET technology node. The proposed OTA benefits from the ballistic transport operation of the GAA-CNTFET transistors at ultra-scaled dimensions which provide a superior bandwidth (2.88 GHz) along with suitable power consumption (44.8 $$\upmu$$ W). The proposed OTA shows a 64.5 dB open-loop gain and a 59 dB common-mode rejection ratio at a 1 V supply voltage. Moreover, due to the utilization of the indirect feedback compensation method, the proposed GAA-CNTFET-based OTA presents an appropriate phase margin (61 $$^{\circ }$$ ) with a smaller compensator capacitor. With the mentioned performance metrics and occupying only 0.198 $$\upmu {\mathrm{m}^{2}}$$ physical area, the proposed GAA-CNTFET OTA has the potential to be considered as a replacement for nanoscale CMOS-based OTAs.

A Maximum Power Point Tracking (MPPT) for PV system using Cuckoo Search with partial shading capability

Component value selection for active filters based on minimization of GSP and E12 compatible using Grey Wolf and Particle Swarm Optimization

A new hybrid optimization algorithm, a hybridization of cuckoo search and particle swarm optimization (CSPSO), is proposed in this paper for the optimization of continuous functions and engineering design problems. This algorithm can be regarded as some modifications of the recently developed cuckoo search (CS). These modifications involve the construction of initial population, the dynamic adjustment of the parameter of the cuckoo search, and the incorporation of the particle swarm optimization (PSO). To cover search space with balance dispersion and neat comparability, the initial positions of cuckoo nests are constructed by using the principle of orthogonal Lation squares. To reduce the influence of fixed step size of the CS, the step size is dynamically adjusted according to the evolutionary generations. To increase the diversity of the solutions, PSO is incorporated into CS using a hybrid strategy. The proposed algorithm is tested on 20 standard benchmarking functions and 2 engineering optimization problems. The performance of the CSPSO is compared with that of several meta-heuristic algorithms based on the best solution, worst solution, average solution, standard deviation, and convergence rate. Results show that in most cases, the proposed hybrid optimization algorithm performs better than, or as well as CS, PSO, and some other exiting meta-heuristic algorithms. That means that the proposed hybrid optimization algorithm is competitive to other optimization algorithms.

Introduction to Circuit Analysis and Design

In the front-end of a conventional pipelined ADC, the embedded multiplying digital-to-analog converter (MDAC) has to meet very stringent noise, speed, and linearity requirements. As a result, the MDAC needs an operational amplifier (OP) with a very high open-loop gain and a large unity-gain bandwidth. Such an OP dominates the overall power dissipation of the pipelined ADC. Moreover, as the advanced technology keeps scaling, the reduced supply voltage limits the signal headroom and the reduced channel length decreases the intrinsic gain of transistors.Consequently, it is very difficult to design an OP that can achieve the stringent specifications with the advanced technology. In order to save power and alleviate the design difficulty in advanced technology,this thesis proposes a 13-bit 100-MS/s pipelined ADC with digital background calibration. The design replaces the conventional closed-loop residue amplifier with a simple open-loop architecture in the first pipelined stage which specifications is the most stringent in the pipelined ADC. The gain error and the third-order nonlinearity of the open-loop residue amplifier are calibrated using a digital background calibration technique. The calibration scheme continuously estimates and calibrates the errors introduced by the imprecise and nonlinear gain of the open-loop residue amplifier. By adopting the concept of digital-assist analog circuit design, this thesis implements a high performance pipelined ADC with the aid of CMOS scaling. The proposed pipelined ADC has been designed and fabricated in a TSMC 0.18-um CMOS process and the digital background calibration is implemented by a FPGA. The measurement results show that the ENOBs of the ADC output with calibration and without calibration at an analog power supply of 1.65V, a digital power supply of 1.8V, and a sampling rate of 12MS/s are 5.3 bits and 7.2 bits,respectively. There are two possible reasons that cause the performance degradation of the pipelined ADC. First, the pipelined ADC can’t work properly and the offset of the backend stage can’t be cancelled because of a timing error of the comparator design. Second, the operating speed of the flash memory on the FPGA board limits the sampling rate of the pipelined ADC to be less than 12MS/s.