Introduction to Circuit Analysis and Design

This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

10 - Basic analog electronics: Operational amplifiers

This paper proposes novel grounded and floating high order series and parallel immittance simulators using operational transconductance amplifiers (OTAs) and operational amplifiers (OAs) with a finite gain–bandwidth (GB) product. They are composed of active devices (OTAs and OAs) and resistances, and are suitable for monolithic implementation in either CMOS or bipolar technologies. They also realize both positive and negative high order immittances. The circuit characteristics can be electronically tuned by adjusting the transconductances of OTAs and the GB products of OAs. Any transfer functions are realizable using the proposed simulators. Two examples are shown, together with simulation results.

A general concern in VLSI design is power efficiency. It is indeed very obvious that battery operated equipment, such as handheld cellular phones, laptop computers etc. impose stringent limits on the acceptable power dissipation. The power dissipation of CMOS circuits is determined at different levels. On the system/architecture level, pipelining, replication, retiming, and bit-serial operation can result in power savings [1]. Moreover, new technologies with smaller feature sizes and lower supply voltages contribute to lowering power dissipation. In this paper author used an extra circuitry that is demultiplexer and an ALU design to explain the concept of reducing power consumption. The technique that author has used in this paper is also applicable for other designs like processor or any other real time process designing.

Energy-constrained measurement systems must simultaneously offer good measurement performance and reduced power dissipation. However, noise in op-amp-based signal amplifiers is usually reduced at the cost of increased supply currents, hence power dissipation. Conversely, low-power op amps are noisier than low-noise op amps. We propose the quotient between the signal-to-noise ratio and the dissipated power as a new figure of merit to evaluate that trade-off in signal amplifiers, and name that quotient the signal-to-noise-to-power ratio (SNPR). We have optimized SNPR for op-amp-based voltage and transresistance amplifiers. If the power dissipated by the feedback current is larger than the op amp quiescent power, the equivalent resistance R p seen from the inverting terminal of the op amp to ground must equal its optimal noise resistance R op (input voltage noise (e n ) divided by input current noise (i n )). Furthermore, a small e n i n product reduces SNPR sensitivity to resistor values that deviate from the optimal value. If the op amp quiescent power dominates over power dissipated by the feedback current, SNPR can be optimized from its graphical representation. The larger is the quiescent power, the smaller is SNPR and the less sensitive is it to R p .

In this research paper, a design for circuit of an operational amplifier (OP-AMP) is formulated utilizing model characteristics of FinFET using high-k gain in the context of 22 nm technological advancements. To create an OP-AMP based on FinFET technology, the standard design equations for MOSFET-based OP-AMP design are tuned to FinFET based OPAMP. The OP-AMP architecture is well-suited for implementation as a subordinate circuit in the ADC design since it supports lower voltage, elevated velocity, and diminished power dissipation. The geometries of the transistors are organised to accomplish an OP-AMP that exhibits superior fulfilment and energy efficiency. Using cadence tool schematic is captured. Results show that the developed OPAMP exhibits a UGB of 100 GHz based on simulation experiments and a slew rate below 10V/µS. The inverter circuit amounts to power dissipation of 800nW, thereby rendering it suitable for a wide range of low-power analog and digital circuits.

In the front-end of a conventional pipelined ADC, the embedded multiplying digital-to-analog converter (MDAC) has to meet very stringent noise, speed, and linearity requirements. As a result, the MDAC needs an operational amplifier (OP) with a very high open-loop gain and a large unity-gain bandwidth. Such an OP dominates the overall power dissipation of the pipelined ADC. Moreover, as the advanced technology keeps scaling, the reduced supply voltage limits the signal headroom and the reduced channel length decreases the intrinsic gain of transistors.Consequently, it is very difficult to design an OP that can achieve the stringent specifications with the advanced technology. In order to save power and alleviate the design difficulty in advanced technology,this thesis proposes a 13-bit 100-MS/s pipelined ADC with digital background calibration. The design replaces the conventional closed-loop residue amplifier with a simple open-loop architecture in the first pipelined stage which specifications is the most stringent in the pipelined ADC. The gain error and the third-order nonlinearity of the open-loop residue amplifier are calibrated using a digital background calibration technique. The calibration scheme continuously estimates and calibrates the errors introduced by the imprecise and nonlinear gain of the open-loop residue amplifier. By adopting the concept of digital-assist analog circuit design, this thesis implements a high performance pipelined ADC with the aid of CMOS scaling. The proposed pipelined ADC has been designed and fabricated in a TSMC 0.18-um CMOS process and the digital background calibration is implemented by a FPGA. The measurement results show that the ENOBs of the ADC output with calibration and without calibration at an analog power supply of 1.65V, a digital power supply of 1.8V, and a sampling rate of 12MS/s are 5.3 bits and 7.2 bits,respectively. There are two possible reasons that cause the performance degradation of the pipelined ADC. First, the pipelined ADC can’t work properly and the offset of the backend stage can’t be cancelled because of a timing error of the comparator design. Second, the operating speed of the flash memory on the FPGA board limits the sampling rate of the pipelined ADC to be less than 12MS/s.

Electro capacitive cancer therapy (ECCT) system are constructed by six sub-systems, in this paper presented design and simulation for two sub-system in ECCT namely frequency generator and amplifier level converter. Design of two sub-system become first study for ECCT system can be applying to the IC technology. Design process begins with understand ECCT standard operation mode signal specification like input signal voltage, output signal voltage, form and frequency. Then using ring oscillator, negative clamper biased, two stage operational amplifier (op amp) circuits that estimated can produce those signal specification and layout them based on BSIM 3.1 MOSFET model using 300nm CMOS technology. Simulation result show that the system layout can produce 19Vpp, 100 kHz and asymmetric output signal from 5 volt DC input signal.

Various key components of mechatronic systems are modeled in this chapter. Dynamic models of actuators of various kinds are modeled with detailed physical relationships. Several examples from mechanical (mechanisms, cam, gear, and belt drives, etc.), electrical (DC, AC, and stepper motors, etc.), magnetic, and hydro-pneumatic actuators are detailed. Thereafter, models for various kinds of sensors (position, velocity, force, pressure, etc.) are developed by using the concept of activated bonds. In the next step, analog electronic circuit components like operational amplifier, diode, and transistor are developed from first principles. Various electronic circuits (op-amp circuits like integrator, Wien bridge oscillator, transistor amplifier and switch, Darlington transistor configuration, Buck converter, etc.) are modeled and analyzed. Bond graph modeling has been used in this chapter to model, analyze, and simulate electronic circuit behaviors.

The main designs of low-sensitivity multiloop active RC filters (ARCFs) based on micropower operational amplifiers (OAs) for preliminary sensor signal processing in microelectronic measuring systems with analog-to-digital converters are discussed. Thirteen modifications of the integrators included in the active RC filter structure are presented and classified. The equations for their transfer functions, which take into account the effect of the integrator topology and the amplification area of micropower OAs, are obtained. As an example, the frequency responses of three universal low-sensitivity ARCF circuits for implementing bandpass, high-pass, and low-pass filters are compared. It is shown by computer simulation that the investigated ARCFs based on identical micropower OAs differ from each other in the effect of the amplification areas of the OAs on the implemented frequency responses.

This uses Wattch and the SPEC 2000 integer and floating-point benchmarks to explore the role of branch predictor organization in power/energy/performance trade offs for processor design. Even though the direction predictor by itself represents less than 1 percent of the processor's total power dissipation, prediction accuracy is nevertheless a powerful lever on processor behavior and program execution time. A thorough study of branch predictor organizations shows that, as a general rule, to reduce overall energy consumption in the processor, it is worthwhile to spend more power in the branch predictor if this results in more accurate predictions that improve running time. This not only improves performance, but can also improve the energy-delay product by up to 20 percent. Three techniques, however, can reduce power dissipation without harming accuracy. Banking reduces the portion of the branch predictor that is active at any one time. A new on-chip structure, the prediction probe detector (PPD), uses predecode bits to entirely eliminate unnecessary predictor and branch target buffer (BTB) accesses. Despite the extra power that must be spent accessing it, the PPD reduces local predictor power and energy dissipation by about 31 percent and overall processor power and energy dissipation by 3 percent. These savings can be further improved by using profiling to annotate branches, identifying those that are highly biased and do not require static prediction. Finally, we explore the effectiveness of a previously proposed technique, pipeline gating, and find that, even with adaptive control based on recent predictor accuracy, pipeline gating yields little or no energy savings.

The conversion of the concept and the teaching of approximation function for analog low pass filter to computer aided numerical class project as an active learning strategy is presented. Governing equations for five approximation functions are presented and discussed. It is recommended that students are tasked to develop computer programs in any convenient computer programming language to make the pole-zero plot, obtain the transfer function, and plot the frequency response of low pass filters. Steps for such programs are suggested. Typical programs were developed and tested. The pole-zero plots and frequency response graphs generated are good illustrative and innovative teaching aids. Linear-phase response over the passband is a characteristic of Bessel approximation function but suffers less amplitude discrimination in the stopband. Chebyshev and Inverse Chebyshev approximation functions have the same order requirement which is usually greater than that of Elliptic approximation function but less than that of Butterworth approximation function. Elliptic approximation function is the best choice although it is more complex than the others. Through this computer aided numerical class project, the authors themselves gained more insight in the subject matter; certainly, students will learn actively.

This paper presents a thermoelectric infrared (IR) sensor which comprise of an infrared detector and a readout circuitry. It is designed by TSMC 0.35 μm CMOS process with subsequent micromachining technology. The presented infrared sensing device can achieve the responsivity of 1277.92 V/W and time constant of 2.63 ms. The instrumentation amplifier (IA) for thermoelectric infrared sensor features a gain of 45.55 dB and a CMRR of more than 90 dB. The operation amplifier (op-amp) for IA realization has a gain of 70.45 dB with an 85 MHz bandwidth and a common-mode rejection ratio (CMRR) of more than 70 dB. The total power dissipation of readout circuit is 11.1 mW and the chip size is 1025×815 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A procedure for the precise determination and compensation of the lead-wire resistance of a resistance transducer is presented. The proposed technique is suitable for a two-wire resistance transducer, especially the resistance temperature detector (RTD). The proposed procedure provides a technique to compensate for the lead-wire resistance using a three-level pulse signal to excite the RTD via the long lead wire. In addition, the variation in the lead-wire resistance disturbed by the change in the ambient temperature can also be compensated by using the proposed technique. The determination of the lead-wire resistance from the proposed procedure requires a simple computation method performed by a digital signal processing unit. Therefore, the calculation of the RTD resistance and the lead-wire resistance can be achieved without the requirement of a high-speed digital signal processing unit. The proposed procedure is implemented on two platforms to confirm its effectiveness: the LabVIEW computer program and the microcontroller board. Experimental results show that the RTD resistance was accurately acquired, where the measured temperature varied from 0 °C to 300 °C and the lead-wire resistance varied from 0.2 Ω to 20 Ω, corresponding to the length of the 26 American wire gauge (AWG) lead wire from 1.5 m to 150 m. The average power dissipation to the RTD was very low and the self-heating of the RTD was minimized. The measurement error of the RTD resistance observed for pt100 was within ±0.98 Ω or ±0.27 °C when the lead wire of 30 m was placed in an environment with the ambient temperature varying from 30 °C to 70 °C. It is evident that the proposed procedure provided a performance that agreed with the theoretical expectation.

Background: The Operational amplifier (op-amp) is the building block of linear integrated electronics, therefore proposing newer design models with improved parameters is an essential landmark in the electronics industry in the hunt for a faster and more efficient design. Objective: To attain high speed and low power supply, the authors designed an op-amp using three different techniques. Initially compensating network was designed and simulated but the resultant output voltage saturates in inverting and non-inverting modes. Methods: Voltage feedback op-amp (VFOA) and current feedback op-amp (CFOA) were proposed to achieve the target. The authors have successfully designed the circuit, but the power dissipated is less and Common Mode Rejection Ratio (CMRR) is high in CFOA in comparison to VFOA. Results: The results are simulated for three different configurations and inverting configuration results in remarkable results in comparison to a non-inverting and differential amplifier. Inverting configuration using VFOA results in 91.22dB, and 0.0131W CMRR and power dissipation, respectively, while that of CFOA results in 97.34dB, and 0.0129W CMRR, and power dissipation, respectively. Conclusion: 1.6% improvement in CMRR and a 26.8% improvement in power dissipated for the proposed CMOS CFOA in comparison to the proposed VFOA. All the validations are done by plotting the bode plot and Nyquist plot.