10 - Basic analog electronics: Operational amplifiers

Chapter 12 - Basic Analog Electronics: Operational Amplifiers

Introduction to Circuit Analysis and Design

Chapter 3 - Development of the Ideal Op Amp Equations

The design of low-frequency filters by means of RC feedback around active elements has long been known. The advent of the transistor has renewed interest in this field and has necessitated a more exact synthesis procedure. This is because in the classical design the active element is assumed to be an ideal voltage amplifier with infinite input impedance, zero output impedance and zero reverse transmission. The transistor satisfies the dual ideal assumptions to a considerably lesser degree than the vacuum tube. The sensitivity of the transistor parameters to temperature also requires more attention to be paid to the effect of parameter variations on the filter response. The paper extends the classical theory in several directions: 1) A synthesis procedure is developed in which the finite input and output impedances and reverse transmission of the active element are taken into account in an exact manner. 2) The freedom that exists is used to optimize the synthesis so as to permit design with a "least active" element. 3) Expressions are developed for the sensitivity of the filter to the four low-frequency active parameters and to the passive parameters. It is presumed that the design specifications include a statement of the extent of active and passive parameter variation and the tolerances on the filter response. The procedure for satisfying such specifications is an integral part of the design procedure. 4) Under the constraint of fixed source and load impedances and desired parameter insensitivity, the design achieves maximum gain. An example which includes all the above features is worked out in detail. The principal limitations of the design procedure are: 1) It is restricted to a transfer function of second degree so that if sharper cut-offs are needed, several basic sections must be used, separated by isolating stages. 2) It is best suited to achieve low-pass or moderate band-pass characteristics.

Chapter 7 - Advanced Transistor Amplifier Techniques

It is well known that real op-amps do not share most of the desirable characteristics of an ideal one, particularly those of gain and output impedance. When presented with a capacitive load, such as a MOSFET or ADC, feedback in an op-amp circuit can quickly become unstable. This thesis studies and characterizes an op-amp’s output impedance and how its interaction with this type of load creates a parasitic pole which leads to instability. Applying ideas from feedback control theory, a model for studying the problem is developed from which a generalized method for compensating the undesirable circumstance is formulated. Even in a zero-input state, many real op-amps driving capacitive loads can experience unforced oscillations. A case study is performed with three commonly used devices. First, the output impedance is determined by its dependence on the unity-gain bandwidth, load capacitance, and oscillation frequency. It is fitted into a second-order feedback control model that allows for an analytical study of the problem. It is then shown that a carefully designed passive network can be introduced between the load and op-amp to obtain a properly damped system free of oscillation and well-behaved. Using a shunt resistor is a known and commonly used method for lowering an op-amp’s output impedance to gain stability. This work considers the converse addition of a series capacitor to instead lower the load capacitance seen by the op-amp, a seemingly complementary method that achieves the same goal. A generalized, composite compensation method is developed that uses both the shunt resistor and series capacitor– a strategy not yet found in literature. Relevant formulas for damping ratio and natural frequency are derived that allow the design of a passive compensation network. Furthermore, tradeoffs between compensation, voltage swing, current consumption, and power usage are considered. An emphasis is placed on comparing simulated versus real circuits to highlight the fact that any problem is much worse in real-life than in a simulation. SPICE models and programs aim to de-idealize certain device characteristics, but often cannot account for environmental conditions and manufacturing variance. Thus, an importance is placed on experimental verification guided by simulations.

Bridges employing inductive voltage dividers are known to be more accurate and more stable than comparable bridges employing resistances as their adjustable elements. Inductive voltage dividers have other desirable properties that have received less attention. Among these are high input impedance, and low output impedance. These secondary advantages are discussed and a typical circuit is solved, both in the balanced and the unbalanced states. It is shown quantitatively that unbalance currents can flow without the necessity of magnetizing the dividers and that this can lead to output impedances that are almost entirely resistive, with negligible reactive components. This desirable state of affairs can exist because magnetic field is a vector quantity and the fields of two currents in an inductor can cancel. Similar possibilities seem to be lacking when resistors or capacitors are used.

CCII-based voltage-mode and current-mode high-order filters with gains and grounded passive elements only

In this paper, we propose an analog-to-digital converter (ADC) using a hybrid single-electron-transistor/complementary metal-oxide-semiconductor (SET/CMOS) universal literal gate based on the Coulomb oscillation phenomenon of a SET. The SET/CMOS universal literal gate consists of the SET/resistor inverter and the CMOS inverter, whose input is connected to the output of SET/resistor inverter. Because the CMOS inverter has the high input impedance and the low output impedance, the proposed circuit makes it possible to overcome the disadvantage of the high output impedance of a SET/resistor inverter by connecting its output to any input of CMOS circuit. The circuit has shown high immunity on temperature and can eliminate the background charge effect as applied to ADC. Using SPICE macromodel of SET at 30 K, we demonstrated the performance of a 4-bit ADC, composed of SET/CMOS universal literal gate and capacitive divider. These results can be simply extended to multi-bit ADC.

A multiple output noninverting op amp circuit which can realize any positive value of voltage gain is presented. The circuit is analysed to find out the voltage gain and output resistance at each output assuming ideal and non ideal op amp.

Analog front-end circuits are essential during the acquisition of sensed biosignals such as during electroencephalography (EEG), electrocardiography (ECG) and electroretinography (ERG). EEG is crucial for diagnosing neurological conditions such as epilepsy, sleep disorders, encephalopathies, and coma. For epilepsy, effective treatment requires precise tracking and profiling of seizures to ensure correct medication administration. Furthermore, accurate seizure characterization necessitates continuous EEG monitoring in a way that does not disrupt a patient's daily activities. Wearable devices are well-suited for this purpose, but their relatively high power consumption limits the duration of continuous monitoring. Hence, there is a need for a low-power analog EEG signal processing system that includes a feature extraction circuit capable of deriving spectral power directly within the analog domain.In EEG signal measurement systems, the instrumentation amplifier is typically the first block of the analog front-end that processes the signals prior to analog filtering and the conversion with an analog-to-digital converter for further digital processing. Hence, being the first block in the system, the reduction of noise levels is of foremost importance during the design of instrumentation amplifiers, especially while reducing their power consumption for portable applications. Another trend is that gel-free electrodes (i.e., dry electrodes) are becoming increasingly popular in long-term EEG monitoring applications due to their practical advantages over wet electrodes. However, the use of dry electrodes is associated with high contact impedance at the skin interface. Therefore, a high input impedance is an important requirement for instrumentation amplifiers in order to acquire EEG signals with high fidelity. This research focuses on the investigation of a new chopper instrumentation amplifier (IA) architecture with a symmetric negative capacitance generation feedback (NCGFB) loop, which is primarily designed to be part of a low-power analog front-end chip for EEG signal monitoring. The purpose of the negative capacitance generation technique is to cancel the parasitic capacitances of the cable and dry electrodes at the IA input in order to boost the input impedance. The negative capacitance is generated through feedback loops containing 9-bit digitally programmable capacitor banks. For prototyping with automated measurements, these capacitor banks are controlled using two machine learning (ML) optimization algorithms, the genetic algorithm (GA) and the particle swarm (PSO) algorithm. These algorithms offer a significant time reduction compared to a calibration with an exhaustive search, reducing calibration time by a factor of over 10^6 (with four 9-bit digital control words) while conserving computational resources. Notably, this dissertation introduces the first use of ML-based techniques for the digital-assisted calibration of an IA's input impedance, marking an advancement in the field of IA design. The GA algorithm achieved an input impedance of 1.7 GΩ after four generations (iterations), while the PSO algorithm achieved 1.3 GΩ with five iterations. A chopping technique was developed to enhance the noise performance of the IA with input impedance boosting. The proposed IA is based on a capacitively-coupled IA (CCIA) architecture with circuit-level innovations for improved noise performance and higher input impedance. It has fully symmetric negative capacitance generation feedback (NCGFB) loops that enable the use of identical NCGFB capacitor banks for common-mode rejection ratio (CMRR) enhancement. The IA was designed and fabricated in 65-nm CMOS technology, and it consumes 2.46 μW from a 1.2V supply. Chip measurements showed that the IA has 44 dB gain, 40 Hz bandwidth, total harmonic distortion of -44.3 dB with a 35 mVpp sinusoidal output at 10 Hz, CMRR > 90.9 dB, a 92.3 dB power supply rejection ratio (PSRR), 0.54-μV integrated input-referred noise over a bandwidth of 0.1-40 Hz with a noise efficiency factor of 4.75, and an input impedance of 1.9 GΩ at 10 Hz even with an extra external capacitance of 100 pF at its inputs.--Author's abstract

This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

A power factor corrected (PFC) Canonical Switching Cell (CSC) converter is proposed for low power consumer light-emitting diode (LED) lighting applications. The proposed CSC converter is intended to operate in discontinuous inductor current mode (DICM) to realize improved power quality performance. In low power consumer lighting applications, the CSC converter is more suitable due to its many benefits such as high energy storing capability, high input and low output impedance as compared to other buck-boost converters. This paper describes the different performance parameters of the proposed converter. Application of lighting load is also examined in view of achieving improved power quality over the wide input AC mains voltage. The measured converter efficiency of a laboratory prototype is found to be 93.8% and total harmonic distortion (THD) of the input current is observed only 6.52% at 230 V AC mains for a prototype of 50 W. Due to less switching losses, the proposed converted has shown much-improved results as compared to the conventional buck-boost converter.

A Ka-band CMOS cascode power amplifier (PA) linearized with a cold-FET-based interstage matching network is presented, which is designed in a 65-nm CMOS process. Since it is difficult to make a cascode PA matched to the optimum output and input impedances at high frequencies, a matching network has to be introduced at the node between the common-source (CS) and common-gate (CG) stages. The cold-FET-based matching network improves the linearity and the input and output impedance matchings, which is analyzed and optimized with its simple model. It makes the PA have gain expansion and phase lag with the power, which allows the PA to have less amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortions. In addition, it improves the return losses of the PA by making the impedances for power matching and conjugate matching located closely. The implemented PA achieves the peak power-added efficiency (PAE) of 38.2% and the saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) of 17.1 dBm at 31 GHz while occupying the chip area of 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It is also shown that the OP1 dB is improved by 1.7 dB, and the AM-PM distortion is reduced to only 1.1° due to the linearization technique. It is tested with 64-quadrature amplitude modulation (QAM) signals, which has a 400-MHz channel bandwidth (BW) and a 9.7-dB peak-to-average power ratio (PAPR). It achieves average output powers of 9.6/7.7 dBm with error vector magnitudes (EVMs) of -25/-30 dB for 64-QAM OFDM signals, efficiencies of 17.7%/12%, and the adjacent channel leakage ratio (ACLR) of -28.2/-32.8 dBc, respectively.

In the paper, a general method of calculating relative errors of Q-factor and ma pole frequency for second order active RC networks is given. The analysis of pole quality and frequency was carried out assuming a two-port model of amplifier with input and output impedances and one-pole gain characteristics, The presented analysis is a generalization of tho Wilson-Bedri-Brown method for active KC networks with operational amplifiers. The general stability condition was determined from relative-errors of Q-factor and ω0 frequency. It was shown that the stability condition of networks with op-ams was a specific case of the general one. The condition for zero relative error of the Q-factor for design procedure of active networks was given. It was shown that for the network designed in such a way the sensitivity coefficient of the Q factor with respect to gain is equal to zero. The analysis and design procedure of the network are illustrated by synthesis of the ‘biquad’ section.