Monolithic Integration of Micro-cantilever with Conditioning Circuits based on SOI Techniques

Review of SiGe HBTs on SOI

As the applications of micro electronic mechanical system (MEMS) are booming, more and more research and development activities are involved in the MEMS industry. For every new MEMS product with new functions, the manufacturing process will be tailored to cope with the changes. This requires reliability work to ensure the robustness of the new process. Thus, failure analysis plays an important role in the process development and the success rate for MEMS FA will be critical. In this paper, we will discuss a new decapsulation approach using a wedge diamond indenter based tool. It is a pure mechanical method and most of all, the whole process can be visually guided and monitored with the onboard optical vision system. The precision knob based operation is controllable, which makes the success rate very high by every user. We have successfully applied this method to our MEMS FA cases and this paper will detail our experiences.

Designing ideal analogue circuits has become difficult due to extremely large-scale integration. The complementary metal oxide semiconductor (CMOS) analog integrated circuits (IC) could use an evolutionary method to figure out the size of each device. The CMOS operational transconductance amplifier (CMOS OTA) and the CMOS current conveyor second generation (CMOS CCII) are designed using advanced nanometer transistor technology (180 nm). Both CMOS OTA and CMOS CCII have high performance, such as a wide frequency, voltage gain, slew rate, and phase margin, to include very wide applications in signal processing, such as active filters and oscillators. The optimization approach is an iterative procedure that uses an optimization algorithm to change design variables until the optimal solution is identified. In this study, different sorts of algorithms the genetic algorithm (GA), particle swarm optimization (PSO), and cuckoo search (CS) are employed to boost and enhance the performance parameters. While decreasing the time required to develop a conventional operation amplifier's settling time. Some studies decrease the value of the power utilized at various frequencies. Others operate at extremely high frequencies, but their power consumption is greater than that of those operating at lower frequencies.

Silicon on Insulator (SoI) technology has tantalized the photonics world in terms of integrated device modeling encountering with numerous applications. Many gas sensors can be designed using SoI technique with lower scaling factor and higher operational speed [1]. The emission of Carbon dioxide is a natural process but excess emisson is a result of burning of fossil fuels, deforestation, increase in the use of automobiles [2]. People who work in automobile industries more likely face the respiratory problems, dizziness etc. To address these issues a gas sensor is designed to detect the excess of emitted CO2. In this manuscript an approach to sense CO2 gas using microring racetrack resonator is demonstrated. The sensing analysis is done on the basis of change in the refractive index (RI) in the cavity region which will result in the envelope spectrum shift.

Selective buried oxide (SELBOX) Metal‐Oxide‐Semiconductor Field‐Effect Transistor (MOSFET) structure can be used to reduce the kink effect and self‐heating problems associated with the silicon on insulator (SOI) MOSFET devices while maintaining the advantages of bulk MOSFET. In this paper, static power dissipation of SELBOX structure is investigated and compared with SOI and bulk structures. Various MOSFET structures are simulated and evaluated in terms of their static power dissipation. Only results from 90‐nm Complementary Metal Oxide Semiconductor (CMOS) technology devices are included in this paper. Simulation results using the Silvaco TCAD show that static power dissipation in SELBOX CMOS is similar to that of SOI devices but lower than that of bulk CMOS. Hence, SELBOX structure is found to produce relatively low‐static power dissipation while maintaining high operating speed and reducing self‐heating and kink effect. A mathematical model to describe the static power dissipation in the subthreshold region is also included. Statistical analysis show that the model and fabrication simulation results agree with P < .05 and correlation coefficient of 0.95.

6 Z REE N°1/2019 LES GRANDS PRIX 2018 DE LA SEE Introduction From the first experimental papers demonstrating the unique features of planar Fully Depleted Silicon on Insulator (FDSOI) for CMOS devices [1], to its industrialization at the 28nm technology node [2], it spent more than 25 years. FDSOI adoption by industry required many innovations brought by ars. FD d m adoption b e triangle of knowledge: education, fundamental research carried out by the tri menta owledge: educati academics and industry ac try. A brief history of SOI FDSOI means Fully Depleted Silicon on Insulator. This technology concerns on on Insulator. This te ogy ted Silicon the basic device at the heart of all integrated circuits: the transistor. The idea grated cir rcuits: the t stor. T eart of here is not to fabricate it on a bulk silicon substrate, but in an ultrathin silicon ubstrat ate, but in ltrathin n a bulk silicon subst layer on top of an insulating silicon oxide layer. In the 1980s it was noticed n the h it was n silicon oxide layer. In that the presence of such an oxide layer would harden electronics against harden ectronics a e layer would e ionizing radiations. Moreover, SOI devices offer interes

Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always been respected. However, electron device challenges are now much more complex. In order to keep Moore's law living, device scaling-down is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples, used at sub-micron scale. This work proposes an investigation of a hybrid CMOS/SET technology, based on gate-all-around silicon nanowires. It is shown that a silicon nanowire can serve two device purposes: first as innovative 3D metal-oxide-semiconductor field effect transistor (MOSFET), and second as single electron transistor (SET). The SET is a solid-state electronic device, which controls the transport of a unique or a few electrons. SET functions are not limited by its nano-scaled structure. The smaller is the better. SET consists of a small conductive quantum dot, called island, connected to two reservoirs acting as drain and source by tunnel junctions. The size of the island should be as small as possible – typical values ranging from 1 to 4nm – in order to have room temperature operation. Electron transport from source to island, and from island to drain is controlled by a capacitively coupled gate. The nano-scale size of the island makes the carrier electrostatic repulsion efficient. This effect is called Coulomb Blockade. SET advantages are an ultra-reduced size and a very low power consumption, while SET challenges are variability related to dimension control and background charge effect, room temperature operation and a reduced fan-out. The first chapter of this thesis introduces ideas of up-to-date MOS and SET devices and shows how to combine MOS and SET to obtain original electronic functions. The second chapter is a discussion of the nanowire as a technology platform for the integration of SET devices and also presents TCAD simulation results. Key contributions are reported in chapter three. This is the original and complete description of the different top-down processes used for the integration of a gate-all-around MOS/SET platform. Samples integrated at the EPFL Center of Microtechnology (CMI) are presented. Different approaches have been studied and used in order to overcome lithographic limitations, and to have a fast and reliable integration at moderate cost. This includes auto-aligned techniques, focused ion beam prototyping, and top-down local-SOI and true-SOI nanowires. The local-SOI technique based on silicon nano-channel wires has given the best results and offers a lot of flexibility in term of wire cross-sections and shapes. Gate-all-around silicon nanowires, obtained by sacrificial etching and self-limited oxidation, with a circular 5nm diameter cross-section have been characterized. Chapter four is the validation by measurements of both SET and MOS devices. Excellent room temperature characteristics have been observed in MOS structures, while both ID-VG Coulomb oscillations and ID-VD Coulomb gap are observed on smaller structures at cryogenic temperature (T<20K). The process described has many advantages in comparison with bottom-up grown wires, such an excellent crystallinity of the channel and ohmic source-drain contacts. Finite elements simulations have also highlighted the influence of carrier mobility, channel length and cross-section shape in our defined nanowire structures. The last chapter of this report concludes this work and gives perspectives on the near future. The hybrid combination of silicon nanowire MOSFET and SET can definitely be an appealing approach in order to bridge the gap between emerging nanoelectronic devices and more traditional CMOS.

We present a study of the effects of substrate orientation and longitudinal channel stress on the performance of extremely thin silicon-on-insulator (ETSOI) MOSFETs with gate lengths down to 25 nm. We find that short-channel electron and hole mobilities follow the long-channel mobility trends versus substrate orientation and longitudinal channel stress. We show that with respect to (100) silicon-on-insulator (SOI) substrates, short-channel ETSOI MOSFETs on (110) SOI substrates lead to 25% enhancement of the p-channel FET drive current at the expense of 12% degradation of the n-channel FET drive current at a fixed off-current of 100 nA/μm and a supply voltage of 1 V. Finally, we estimate that an ETSOI complementary metal-oxide-semiconductor (CMOS) on (110) SOI substrates should lead to 10% faster ring oscillators compared with those on (100) SOI wafers, which also implies that (100)-oriented wafers with (110) sidewalls are a better choice for fabricating nonplanar FinFETs and trigate CMOS circuits.

Nanoresonator systems have been fully integrated on pre-processed complementary metal oxide semiconductor (CMOS) chips. The systems have been used for high sensitivity mass sensing in air and vacuum. The resonator system, which consists of a cantilever and structures for electrostatic actuation and capacitive read-out, has been defined by low energy electron beam lithography (EBL) combined with direct write laser lithography (DWL) on top of a radiation sensitive CMOS layer. The fabrication of the nanoresonator system has been conducted as a post-process step. CMOS integration radically decreases the parasitic capacitance, enabling detection and amplification of the resonance signal directly on the chip. Fabricated resonator systems have been designed to have resonance frequencies in the range of 1-1.6 MHz. A mass resolution of 3 ag/Hz has been determined in air by placing a single glycerine drop at the apex of a cantilever and subsequently measuring a frequency shift of 14.8 kHz. The frequency shift corresponds to an added mass of 50 fg, which is close to the estimated weight of 41 fg for the glycerine drop.

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K.

Resistive humidity microsensor with circuit manufactured by the CMOS process

Cost reduction in optoelectronic packaging requires a high component integration level while maintaining flexibility of design. We present a novel technology approach combining cost effective hybrid integration and local hermetic packaging of active devices like laser diodes or photodiodes, and passive planar optical components, so called Planar Lightwave Circuits. The demands on alignment accuracy between the devices can he met by using flip-chipped lasers and mechanical taper shuctures. Localized hermetic sealing on the PLC in the area of the mounted active device allows for small form factor packaging solutions. The sealing is obtained by soldering of a structured silicon Micro Electronic Mechanical System (MEMS) device with electrical feed-through connections to operate the active device. The paper focuses on the processing and use of mechanical precision alignment structures and the encapsulation of optical devices by Si-MEMS caps for hermetic sealing.

The micro inertial measurement system (MIMS) integrates measurement, sampling, quantization, coding/compression, and storage. It can be used in the measurement of dynamic data in rockets, missiles, and vehicles. It can also monitor, collect, and record data from the human body and ambient environment, and then provide output to a hard disk through a computer interface. These data will later be used to analyze human health. MIMS, which comprises a micro electronic mechanical system (MEMS) transducer, a signal acquisition module, a data compression module, a control circuit, and memory can be used in a variety of applications with different environments and requirements. Volume, cost, and reliability are some of the design variables that we considered. Our research on the MIMS includes a single-chip accelerometer and angle-rate transducer, a novel attitude algorithm and its ASIC, and buffer technology for high-acceleration overload.

A micro FET-based immunosensor was developed for the determination of hemoglobin-A1c (HbA1c). The HbA1c/hemoglobin ratio is an important index in diabetes control. The sensor was fabricated by Complementary Metal-Oxide-Semiconductor Transistor (CMOS) and Micro Electronic Mechanical System (MEMS) techniques. The antibodies were immobilized via mixed self-assembled monolayers (SAMs) on a gold nanofilm. The nanofilm was deposited on a gold electrode by seed-mediated growth and gave a uniform and well distributed coverage. Nonspecific sites and interferences by noise were eliminated by covering the AuNPs with mixed SAMs. Compared to the immunosensor fabricated via the mixed SAMs method without gold nanofilm, the immunosensor displays a more than 2-fold sensitivity. The immunosensor is capable of detecting HbA1c and hemoglobin in hemolyzed and diluted whole blood, and results showed good agreement with the established clinical method.

A SOI (silicon-on-insulator) process using ELO (epitaxial lateral overgrowth) is presented that can be used not only to create local area SOI islands but full wafer SOI as well. A thin full-wafer SOI structure formed with merged ELO has been demonstrated. With minor modification, this SOI process can be successively repeated to produce multiple layers of SOI for future three-dimensional application, since ELO has the advantages of low-temperature processing, ease of interlayer connection, and low cost. This process produces SOI material of very low defect density by using selective epitaxial growth of silicon as compared to other conventional SOI techniques. >