12-nm Stable Pre-Amplifier Physical Unclonable Function With Self-Destruct Capability

A new concept for Physical Unclonable Functions (PUFs), the Mirror PUF, is proposed. The Mirror PUF can be applied to existing preselected PUF circuits by post-processing the preselection test results and has the potential to double the number of effective bits, with no additional area at the bit-cell level. The Mirror PUF utilizes a preselection test, which measures the amount of mismatch within the PUF cell. This data is generally used to determine the mask for a conventional PUF. Here, it is used as an entropy source that is not correlated to the original response of the PUF. Bit-cells with low mismatch are considered as a ‘0’ and cells with high mismatch as a ‘1’. A systematic method is shown for identifying unstable bits in the Mirror PUF response. It classifies the cells to ‘low’, ‘medium’ and ‘high’ mismatch, such that medium mismatch bits are considered as unstable and masked from the response. The concept was applied to a 65nm Si implementation of the Capacitive Tilt PUF (Shifman et al., 2020). All of the unstable cells of the Mirror PUF, except for 0.03%, were identified and masked, with a worst-case corner Bit Error-Rate (BER) of only 2.35E-5 and 0.00026% erroneous responses across all corners. The application of the Mirror PUF to the Capacitive tilt PUF increased the number of stable response bits by 66%. No observable correlation was found between the responses of the original PUF and the Mirror PUF.

Physical Unclonable Function (PUF) is recently used in modern electronic systems for device authentication and secret key generation. SRAM PUF is a popular memory-based PUF because it is a standard component for most electronic devices. Previously only strongly stable RAM bits are selected as PUF bits in order to achieve high reliability, hence requiring relatively large SRAM. Furthermore, SRAM PUF might suffer from PUF clone attack for using stable bits. Attackers may use Photon Emission Analysis (PEA) to observe the behavior of the stable bits and conducted Focused Ion Beam circuit edit (FIBCE) to produce an identical physical response. In this paper, we propose a new method that employs unstable bits as PUF bits in addition to the stable bits to increase the SRAM bit usage rate. We also show that this method can efficiently resist the PUF clone attack. Experimental results show that even though our proposed method uses unstable bits as PUF bits, it can still achieve high reliability. It can reach an average 2% intra-HD without Error Correction Code (ECC) under various conditions and an average inter-HD of 49.33%.

This brief presents a NOR-structured physically unclonable function (PUF) tailored for low-cost Internet of Things (IoT) applications. The proposed NOR-structured PUF utilizes a single minimum-sized differential NMOS pair, capitalizing on threshold-voltage mismatch as the entropy source. Fabricated in 65nm CMOS, the basic PUF cell is a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$58F^{2}$ </tex-math></inline-formula> differential NMOS pair, demonstrating a raw bit error rate (BER) of 0.31%. To further enhance the stability and achieve an ultra-low BER, we introduce an area-efficient redundancy strategy. By incorporating 4x redundancy cells (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$266F^{2}$ </tex-math></inline-formula> in total), the prototype chip achieves an ultra-low BER (zero error in 20M bits), over a wide temperature range (−20 to 125°C) and supply voltage variations (0.8 to 1.2V). The core energy consumption is only 63fJ/bit, offering a low-cost and highly stable solution for IoT applications.

Physically unclonable function (PUF) has been rapidly developed as a lightweight and tamper-evident on-chip key generation module for a wide range of hardware-security-oriented applications [1] –[6]. Most traditional PUFs' raw output bits, which are susceptible to the temporal noise and environmental voltage-temperature (VT) variations, need to be well-stabilized using temporal/spatial majority voting, burn-in and dark (unstable) bit masking, etc. [1] –[5], in order to alleviate the design overhead of the error correction codes (ECC) at the following stage. Among these stabilization techniques, dark (unstable) bit masking has been demonstrated to be more efficient [1] –[4]. However, constrained by the weak mismatch of regular MOSFETs, a high ratio of raw PUF bits (25%$\sim $67%) have to be discarded to achieve a bit error rate (BER) close to 0%, leading to inferior area efficiency of the bit-cell array [2] –[4]. A relatively low masking ratio of 3.64% is reported in [1] by linearly amplifying the presented hybrid PUF's in-cell mismatch, unfortunately, at the expense of a huge bit-cell of 21675F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (10.2$\cup$m× 3.4$\cup$m) using 40nm CMOS.In addition, non-MOSFET devices exhibiting larger mismatch have been exploited to improve the PUF's reliability at the very first entropy source stage [5], [6].In [5], a metal-silicon-contact-based PUF is presented by designing the contact hole size smaller than the design rule of the adopted process, however, sufficient randomness cannot be guaranteed without adding a two-step XOR operation, which is intrinsically a kind of post-processing-based non-physical entropy. Another highly-reliable PUF with low native BER of 6x1$0^{-6}$ is reported based on the emerging resistive-random-access-memory (RRAM) devices configured to the high resistance state (HRS) [6], nevertheless, the necessity of post-CMOS processing steps dedicated to the RRAM devices makes the standard-CMOS-based low-cost implementation infeasible.

Physical unclonable functions (PUFs) are widely researched security primitive in the digital and analog domain but have yet to be explored for asynchronous circuits. In this paper, we propose novel optimization methods to design a weak Asynchronous RESet (ARES) PUF that exploits random start-up characteristics of Threshold M of N Null Conventional Logic (NCL) gates as a source of entropy. We employ two different methods to design the ARES PUF. The first includes traditional delay matching techniques using linear programming-based optimization, whereas the second one uses the genetic algorithm (GA) with delay matching as a fitness function. Both methodologies are explained with analysis and design specifications required to model NCL TH22 gates to achieve PUF characteristics. Threshold 2 of 2 (TH22) and 4 of 4 (TH44) gates are used as test cases for evaluation and comparison. Simulation results using initial delay matching techniques at 90nm and 65nm technology in HSPICE shows that the proposed ARES PUF has a uniqueness of 49.98% and reliability of 96.53% across VDD variation (±10%) and 93.39% across temperature variation (0°C-80°C). Whereas, the GA method can optimize NCL cells to form a PUF with 49% uniqueness at 65nm with an average reliability of 96.4% across VDD and 93.82% across temperature. Preliminary silicon results for proposed TH22 at TSMC 90nm technology node shows a 34% improvement in uniqueness compared to standard TH22 gate with best-case uniqueness of 53.3% and reliability of 100% respectively across repeated measurements (noise). Unlike standard TH22, standard TH44 performs better with 47.62% best-case uniqueness and 98.1% reliability <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .

A Physical Unclonable Function (PUF) is a die specific random function that can be used in a number of secure IC applications including die identification/authentication and key generation. At the core of a silicon PUF is a circuit (the PUF core) that generates random bits. These bits are like a silicon biometric, unique across dies, but can be reliably reproduced multiple times on a die across voltage and temperature variations and aging. In this thesis, we discuss various aspects of a PUF design, with a strong focus on circuit details. We describe the properties and the figures of merit of a PUF and then compare various PUF core implementations. We identify the biggest design challenges and provide several solutions. Results in this work are supported by measurement data from testchips designed in 65nm bulk CMOS. We provide an apples-to-apples comparison of various PUF implementations. We demonstrate that while adequate randomness and uniqueness is achievable for most PUF implementations, achieving high reliability is a challenge. The conventional method to achieve high reliability is to use error correcting codes (ECC). Unfortunately, the overheads associated with these techniques grows very quickly with error correction capability. Alternately, researchers have proposed several error reduction techniques to minimize the use of error correction. In this work, we evaluate four orthogonal and complementary error reduction techniques. Two of these techniques, categorized as extrinsic techniques, are multiple evaluation (ME) and activation control (AC) and are able to reduce errors in PUF response by ~70-80%. The other two techniques, categorized as intrinsic, are post-silicon selection (PSS) and directed accelerated aging (DAA) and show ~100% correction of errors. As a proof of concept prototype, we describe a self-contained, BIST-controlled key-generator that implements the PSS technique to autonomously generate bits with a bit error rate &lt; 5 * 10^-9, equivalent to a 128-bit key error rate &lt; 10^-6. We also describe a realization of a strong-PUF that uses these highly reliable bits in conjunction with an Advanced Encryption Standard (AES) primitive.

Physically unclonable functions (PUFs) have been explored as lightweight hardware primitives for the purpose of realizing robust security via strong authentication or secure key/ID generation. PUF harness manufacturing process variations for the purpose of generating binary keys or binary functions. An ideal strong PUF is a binary function that maps an m-bit input challenge to an uniquen-bit output response, making it attractive for authentication applications. Unfortunately, real strong PUF implementations suffer from reliability issues where the same challenge may produce different responses in the presence of noise. To overcome this problem, strong PUF leverages the availability of exponential number of challenge-response pairs (CRPs). A successful authentication event requires acquiring multiple CRPs and applying a threshold. In contrast, weak PUFs produce limited keys and are required to be highly reliable. Multiple techniques have been developed to achieve the necessary reliability. An additional prerequisite for strong PUFs is resilience against model-building attacks (cloning) by an adversary, who has observed a few CRPs, to prevent successful prediction of future CRPs. In this work, we first illustrate a strong PUF design that re-purposes a weightless neural network (WNN). Second, we showcase the robustness of WNN-based strong PUFs with respect to machine learning attacks, while providing desirable uniqueness and reliability metrics. Finally, we employ an initial entropy source of highly reliable weak PUF bits mapped to weightless neural networks (WNNs) for the purpose of creating a near-ideal strong PUF in terms of reliability. Our results show that it is possible to create highly reliable WNN–based strong PUFs with < 65 % ML accuracy by using as few as 32 initial reliable weak PUF bits.

Objectives. The purpose of the study is to examine the operational characteristics of a digital circuit designed to analyze the output signal frequency of a configurable ring oscillator within a fixed measurement window. Methods. Methods of digital device synthesis and analysis were employed, including implementation on programmable logic integrated circuits (FPGAs), fundamentals of digital circuit design, and methods for analyzing normally distributed random variables. Results. A digital circuit for recording the period of a configurable ring oscillator, depending on the measurement time window and the value of its configuration has been developed. Experimental studies of the generated signal periods were conducted using Xilinx ZYNQ 7000 series FPGAs. It was demonstrated that upon repeated period measurements the bits of the recording counter can be categorized into three groups: group G 2 : stable bits retaining constant values across all measurements; group G 1 : weakly stable bits exhibiting minor distortions; group G 0 : strongly unstable bits with a distortion probability approaching 1 between measurements. It was hypothesized that group G 0 represents the digitized noise component of the measured period value. Due to numerous independent factors (components within the configurable ring oscillator and digital recorder, supply voltage deviations, die and ambient temperature variations, quantization errors, etc.), it is assumed that this noise component follows a normal distribution. Analytical proof established that a normally distributed variable, quantized using multi-bit binary numbers under specific values of mathematical expectation μ and standard deviation σ , generates only two groups: G 2 and G 0 . It was proven that the probability of a '1' appearing in any bit of group G 0 approaches 0,5, and the group size can be estimated as 3+ ⌊log 2 σ⌋. The bits of group G 1 can be converted to group G 2 using various methods, such as maximum likelihood estimation or by normalizing each measurement value to a theoretically justified separation into G 2 and G 0 . The values of group G 2 bits can be interpreted as a response to a challenge defined by the ring oscillator circuit configuration and measurement window, forming a novel type of multi-bit Physical Unclonable Function (PUF) characterized by high stability. Conversely, the G 0 bits can serve as single-bit sources of random variables with near-uniform distribution, providing a foundation for building random number generators. Conclusion. The obtained results can be utilized in embedded systems for providing unclonable identification of digital devices and for random data generation. The application of a synchronous binary counter as a frequency recording circuit for a configurable ring oscillator opens new avenues for designing multibit physical unclonable function architectures with enhanced performance metrics in terms of stability, uniqueness, and randomness.

Security primitives ensure Internet of Things (IoT) security by generating stable keys from physically unclonable functions (PUFs) and unpredictable bitstreams from true random number generators (TRNGs). Considering the restricted resources on IoT motes, a promising design trend is to unify PUF and TRNG by sharing the same entropy source and multiplexing entropy extractor. Here, we report a unified PUF and TRNG chip based on a 28-nanometer embedded memristor with concealable ability. We use the memristor intrinsic FORMING condition variation and read current variation as entropy sources and design a compact on-chip entropy extractor that achieves a high throughput of 41.7 megabits per second with minimal area overhead of 0.291 MF2. To prevent PUF data leakage, we developed a concealment method, protecting data when idle and enabling recovery upon demand. Comprehensive testing shows the chip has excellent performance in randomness, reliability, lifetime, and stability, achieving a 3.82-fold throughput improvement over complementary metal-oxide semiconductor-based designs in authentication tasks.

The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly eliminate data remanence and maximise physical mismatch. Moreover, a two-phase power gating module is devised to provide controllable power on/off cycles for the chosen PUF clusters in order to facilitate fast statistical measurements and curb the in-rush current. The architecture and hardware implementation of the power-gated PUF are developed to accommodate fast multiple evaluations of PUF Responses. The fast speed enables a new data processing method, which coordinates Dark-bit masking and Multiple Temporal Majority Voting (TMV) in different Process, Voltage and Temperature (PVT) corners or during field usage, hence greatly reducing the Bit Error Rate (BER) and the hardware penalty for error correction. The designs are based on the UMC 65 nm technology and aim to tape out an Application-Specific Integrated Circuit (ASIC) chip. Post-layout Monte Carlo (MC) simulations are performed with Cadence, and the extracted PUF Responses are processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion in PUF Responses, which comprise the novelty of this approach.

A chaotic entropy source based physical unclonable function (PUF) is proposed for the secure and low-power IOT platform. PUF is used to generate an encrypt key for data integrity of each transaction on IOT chain and device ID authentication to secure identification. The PUF use the true-random entropy source based on chaotic characteristics. Entropy core occupies 0.0045 ㎟ in 0.18 μm CMOS technology and consumes 65 nW at 270 kbps throughput with 0.6 V supply. The proposed Entropy Source passes all NIST tests.

Data-dependent half-select free GSRAM cell with word line write-assist and built-in read buffer schemes for use in PUFs-based IoT devices

Memristive physical unclonable function (PUF) is a recent entry to the list of security primitives, employing the intrinsic randomness of memristors. Although this represents a huge opportunity for memristors, all present memristive PUFs suffer from the problem of being device intensive because their entropies come exclusively from the spatial dimension. Here, a temporal PUF (TPUF) is reported, using the randomness of temporal dynamics of memristors as an entropy source. By exploiting temporal complexity, significant reduction of hardware overhead is achieved in the TPUF, from otherwise at least hundreds‐of‐memristors‐scale crossbar arrays to only a pair of memristors. This efficient and cheap TPUF can generate more than 10 37 64‐bit challenge–response pairs (CRPs), whose number is infinitely up‐scalable (in principle) without hardware resource restrictions. Experiments have demonstrated that the TPUF has nearly ideal uniformity, diffuseness, uniqueness, low bit error rate, and NIST‐standard‐quality randomness. In addition, its hard‐to‐learn CRP relationship, forbiddingly large number of CRPs, and the potential slow‐down of the read‐out process make it highly resistant to machine learning attacks. This work represents a new opportunity for memristors for encryption.

Authentication is the act of proving that an integrated circuit (IC) is not counterfeit. One application of a physical unclonable function (PUF) circuit is to authenticate the identity of the chip using raw bits of the memory. However, several previous works present machine learning-based modeling attacks on PUFs. To alleviate this issue, we propose a novel authentication scheme involving unique DRAM power-up values using a deep convolutional neural network (CNN). This methodology eliminates the need for PUFs and can authenticate DRAM technology accurately with a neural network. Our approach converts raw power-up sequence data from DRAM cells into a two-dimensional (2D) format to generate a DRAM image structure. This makes it harder for an adversary to use machine learning since there is no PUF to exploit the weaknesses. Then, we apply deep CNN to DRAM images to extract unique features from each chip and classify them for authentication. Our method “DRAMNet” achieves 98.84% accuracy and 98.73% precision. The proposed technique has the advantage of a faster authentication while eliminating the need for costly error correction mechanisms and CRPs. To the best of our knowledge, this is the first method to authenticate ICs using DRAM and CNN.

In this article, a novel subthreshold voltage reference (VR)-based physical unclonable function (PUF) is presented. With two native nMOS transistors stacked on top for providing bias current and two bottom low threshold voltage (LVT) nMOS transistors forming the self-cascode MOSFETs structure, a 4T all-MOSFET VR is proposed, which features low power consumption and high stability under largely varied VT conditions for the wide range of Internet of Things (IoT) applications. By integrating a pair of the proposed VRs and a digital voltage comparator in each PUF cell, the mismatched output voltages of the VR pair can be locally compared and digitized immediately with the system's power on, leading to ultrashort signal path and maximized immunity to the influence of temporal noise. Fabricated using standard 0.18- μm CMOS process, the proposed PUF design is validated based on extensive measurement results of 20 PUF chips. By passing the widely exploited bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test, the proposed PUF's excellent randomness is well-verified. In addition, the uniqueness is measured to be 49.92%, and the bit error rate (BER) sensitivities in terms of BER per 10 °C and BER per 0.1 V are averaged and reported to be 0.39% and 0.26%, for the temperature range of -40 °C-120 °C and supply voltage range of 1.2-1.8 V, respectively. Moreover, by operating the proposed implementation at a throughput of 50 Mb/s, the measured overall energy consumption is reported to be as low as 163 fJ/bit.