Generation of Deterministic Identifiers and Random Numbers Using a Configurable Ring Oscillator Circuit

Physical Unclonable Function (PUF) is recently used in modern electronic systems for device authentication and secret key generation. SRAM PUF is a popular memory-based PUF because it is a standard component for most electronic devices. Previously only strongly stable RAM bits are selected as PUF bits in order to achieve high reliability, hence requiring relatively large SRAM. Furthermore, SRAM PUF might suffer from PUF clone attack for using stable bits. Attackers may use Photon Emission Analysis (PEA) to observe the behavior of the stable bits and conducted Focused Ion Beam circuit edit (FIBCE) to produce an identical physical response. In this paper, we propose a new method that employs unstable bits as PUF bits in addition to the stable bits to increase the SRAM bit usage rate. We also show that this method can efficiently resist the PUF clone attack. Experimental results show that even though our proposed method uses unstable bits as PUF bits, it can still achieve high reliability. It can reach an average 2% intra-HD without Error Correction Code (ECC) under various conditions and an average inter-HD of 49.33%.

A new concept for Physical Unclonable Functions (PUFs), the Mirror PUF, is proposed. The Mirror PUF can be applied to existing preselected PUF circuits by post-processing the preselection test results and has the potential to double the number of effective bits, with no additional area at the bit-cell level. The Mirror PUF utilizes a preselection test, which measures the amount of mismatch within the PUF cell. This data is generally used to determine the mask for a conventional PUF. Here, it is used as an entropy source that is not correlated to the original response of the PUF. Bit-cells with low mismatch are considered as a ‘0’ and cells with high mismatch as a ‘1’. A systematic method is shown for identifying unstable bits in the Mirror PUF response. It classifies the cells to ‘low’, ‘medium’ and ‘high’ mismatch, such that medium mismatch bits are considered as unstable and masked from the response. The concept was applied to a 65nm Si implementation of the Capacitive Tilt PUF (Shifman et al., 2020). All of the unstable cells of the Mirror PUF, except for 0.03%, were identified and masked, with a worst-case corner Bit Error-Rate (BER) of only 2.35E-5 and 0.00026% erroneous responses across all corners. The application of the Mirror PUF to the Capacitive tilt PUF increased the number of stable response bits by 66%. No observable correlation was found between the responses of the original PUF and the Mirror PUF.

A Physical Unclonable Function (PUF) is often used to uniquely identify an integrated circuit by extracting its internal random differences using so-called Challenge Response Pairs (CRPs). As CRPs include unique information about the underlying hardware variations, PUF design is a promising approach to provide authentication and IP-protection capabilities. In this paper, an XOR-gate-based configurable Ring Oscillator (RO) PUF (denoted as XCRO PUF) is presented. This XCRO PUF can generate more CRPs compared with state-of-the-art PUF designs by using the same number of configurable logic blocks (CLBs) in an FPGA implementation. This design is implemented in the Xilinx Spartan-6 XC6SLX9 FPGAs with fixed locations for the XCROs (placed within a ring to improve its uniqueness). The XCRO PUF shows better uniqueness and reliability than other PUF designs. Moreover, a XCRO PUF consumes only 12.5% of the hardware resources to generate a 1-bit response compared with other CRO PUFs implemented in FPGA.

A novel configurable ring oscillator PUF with improved reliability using reduced supply voltage

Physical Unclonable Functions (PUF) are an emerging hardware security primitives proposed by various researchers in last one decade. PUFs are useful security architectures used for identification, authentication and cryptographic key generation. Many PUF topologies are proposed in the past targeting both ASIC and FPGA. It is nearly impossible to get two PUF circuits with same characteristics for the same design. PUFs make use of random process variation occurring during manufacturing of IC which is uncontrollable. The most versatile PUF is ring oscillator (RO) PUF, in which the frequencies of ring oscillators are compared to produce the PUF response. The conventional approach consumes large number of ring oscillators and requires all RO's to be mutually symmetric. In this paper, we have proposed a RO-PUF for FPGA devices, which is capable of generating multiple output bits from each ring oscillator with better security metrics in comparison with PUF designed with similar technique. The PUF is implemented on Xilinx Spartan 3E FPGA boards and the challenge-response pairs (CRP) are verified for statistical properties.

A lightweight key renewal scheme based authentication protocol with configurable RO PUF for clustered sensor networks

Physical unclonable functions (PUFs) produce full security keys without needing to store the key directly in nonvolatile memory (NVM) or publicly. PUFs rely on a stable entropy source across voltage, temperature, and lifetime. A high-gain preamplifier (Pre-Amp) bit cell was built into a dense 2-D array configured as 16 cells per bitline (BL) and 64 cells per wordline (WL). A hardware (HW) sample of 40 chips (1 Kb/chip) was manufactured in GLOBAL FOUNDRIES (GF) 12-nm (12 lp) CMOS technology for a total raw bit count of 40 960 bits. HW characterization was performed to support power supply ranging from 0.7 to 1.0 V and junction temperatures ranging from −40 °C to 125 °C with a worst case bit error rate (BER) of 0.174% after stabilization. The entropy source array is complete for productization with control logic and analog power system block for process, voltage, and temperature (PVT) compensation. A stable bit identification and sensing circuit is designed to identify bit cells that are robust against varied test conditions. The NIST 800-90B test suite was run on the native array and stable entropy source bits with minimum entropy scores of 0.65/bit and 0.697/bit, respectively. This article then introduces for the first time ever the ability for a PUF key to be corrupted and physically destroyed, which can be utilized to stop a tamper event or to corrupt obsolete chips. In the self-destruct (SD) mode, the entropy source data can be irreversibly destroyed, blocking all future authentication attempts. HW data show the before and after SD bitmaps, where electromigration (EM) physically breaks the connection of the entropy source bit cells from the sensing circuits. A safety lock circuit is also included to prevent inadvertent SD.

In this paper, a new Physically Unclonable Function (PUF) has been implemented and tested. The idea behind this PUF is to compare the bias of the same Galois ring oscillator implemented in different locations within the FPGA. The implemented PUF has been compared to a Ring Oscillator PUF in terms of reproducibility, random-like response and uniqueness. Furthermore, the spatial correlation of the bias of the Galois oscillators has been studied and compared to the spatial correlation of the frequency of regular ring oscillators.

Physical Unclonable Function (PUF) is one of the most promising hardware features that can be utilized to improve system security. Ring Oscillator (RO) PUF captures the delay difference of a pair or a group of ROs introduced during fabrication process and defines PUF secrecy based on such difference. In this paper, we propose a framework to build RO PUF at inverter level, instead of RO level. This provides us the flexibility in choosing whether an inverter should be included in the RO-PUF and hence improve the security and reliability of RO PUF secrecy and reduce its hardware cost. Experimental results demonstrate that the PUF secrecy generated by our configurable RO PUFs is random (by passing the NIST randomness test) and unique from chip to chip. Our approach is more reliable against voltage and temperature variation than the original RO PUF and is 4X more hardware efficient than the robust 1-out-of-8 RO PUF.

In FPGA, routing hotspot affects ring oscillator (RO) performance. The significant difference in routing hotspot between RO locations eliminates physical variation, which is the identity of Physical Unclonable Functions (PUF). This study compares the performance of conventional and uniform routing hotspot RO in Cyclone V chips. For this purpose, ROs and counters are placed in 10 adjacent locations. RO frequency at all locations was measured by a Digital Discovery II, a PC based logic analyzer. In the conventional design, there are significant differences in routing hotspot among RO locations. Meanwhile, in a uniform design, the difference in routing hotspot has been reduced by relocating several logics around specific locations. As a result, the reliability of the conventional design is higher than the uniform routing hotspot design when implemented with 11-stage RO (RO11) and 20-stage RO (RO20). However, the uniqueness of the uniform routing hotspot is better than the conventional ones. Furthermore, the uniformity of the uniform routing hotspot design is closer to the ideal in 20-stage. Conversely, in the 11-stage implementation, the closer uniformity to the ideal is obtained using a conventional design.

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator, in field programmable gate array (FPGA) is crucial replacement of the conventional decryption key stored in battery-backed random access memory or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (Pi-coPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single-slice disorder-based security entities have been investigated and compared on 28-nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bit-aliasing and min-entropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the min-entropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF and some existing memory-based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design are made publicly available to enable the research community to use them for benchmarking and/or validation.

Physical unclonable function (PUF) is regarded as an emerging solution for reliable cryptography. Rather than storing secret keys in memories, the information of a PUF is extracted through amplification of the physically uncontrollable process variations and therefore, can uniquely authenticate each die to counteract counterfeit, piracy or sabotage. Classically, PUF architectures have exploited process variations affecting transistor-level active device performances such as process-dependent gate delays and interconnect delays, SRAM and inverter maximum gain points, and ring oscillator frequencies [1]-[6]. While active device variations have been exploited to generate PUF signatures, they are susceptible to noise, external perturbations and aging. Since the resultant process variant responses are typically normally distributed, to spread the variance of the distribution and decrease the number of challenges near the unstable decision region, we propose a method to exploit passive variations within the chip in addition to active device variations. While lithographic variations in the smallest metal features may not influence the electrical performance drastically, their effects can be amplified at optical frequencies with wavelengths comparable to the minimal feature size. In fact, before the concept of electronic PUFs were demonstrated in silicon, one of the first implementations of strong PUFs was demonstrated in the optical domain, which exploited speckle-patterns of a random scattering medium in the presence of a laser light. In this work, we present the first CMOS-based opto-active PUF, which not only utilizes the active variations, but also amplifies the lithographic variation of passive metal structures through process-sensitive copper-based CMOS integrated photonic crystals. The measured CMOS chip achieves a native Inter-PUF/Intra-PUF Hamming Distance (HD) ratio of 198X without any post-operation.

Embedded systems carry and process more and more sensitive information in untrusted environments, where an attacker can wiretap the external communication and also has unlimited physical access to the device. Cryptography protects systems against many of the threats and relies on the security of the cryptographic keys inside the system. Physical Unclonable Functions (PUFs) measure manufacturing variations inside integrated circuits, for example FPGAs, to generate a unique secret PUF response inside each device. Similar to deriving a biometric pattern from human features, the individual pattern inside an FPGA differs slightly from measurement to measurement. From these measurements, the PUF response is generated to derive a secure and reliable cryptographic key. The Ring-Oscillator (RO) PUF is a popular PUF type because of its high randomness and reliability. Frequencies of ROs are compared pairwise to derive one secret bit. So far, the reliability of RO PUFs was evaluated by counting bit flips in measured PUF responses. This work analyzes the distribution of frequency measurements to derive the behavior of the PUF. Analyzing the frequency distributions gives a more precise estimation of the PUF bit error rates than measuring the bit errors after the comparison of two oscillator frequencies. The evaluation of publicly available real world empirical FPGA data has shown that most error probabilities of RO PUF responses are so low that they cannot be measured in feasible time. For almost 200 evaluated FPGAs, more than 70% of the PUF outputs on every FPGA have bit error probabilities under 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-20</sup> . We can even ensure this error probability for over 60% of the PUF outputs after a practicable number of frequency measurements with a confidence of 99.9%. Index Terms-Physical Unclonable Functions (PUFs), Ring Oscillator PUF, FPGA, Statistics.

Silicon physically unclonable functions (PUFs) are circuits that exploit modern manufacturing variations to generate unique signatures for chip authentication and cryptographic key generation. Existing research has focused on improving PUF quality at architectural or design levels, but has ignored opportunities available during fabrication, which is the source of systematic and random variation in (ICs)/PUFs. For typical ICs (where security is not a concern), optical proximity correction (OPC) is used to suppress both these types of variations. However, several prior works have shown that only systematic variations negatively impact PUF quality and random variations are beneficial for PUFs. In this paper, we propose two PUF-aware OPC cost functions: 1) P-OPC generates a PUF lithography mask that increases all variations in PUF circuitry (the opposite of state-of-the-art OPC), and 2) SVC-OPC generates mask patterns that reduce the systematic variation found in PUFs for better quality. Simulation results for ring oscillator (RO) PUFs show that the proposed techniques can improve PUF signature quality compared to current state-of-the-art OPC.

Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF