16‐2: Cost‐effective Driver IC Architecture using Low‐power Memory Interface for Mobile Display Application

One challenge of high-voltage CMOS process, which is a very important technology for field emission display(FED) driver IC, is DGO(dual gate oxide) technique. The DGO technique means the integration of both thin and thick gate oxide devices on the same chip. In this paper, one sidewall formation is added in DGO technique; the SEM picture shows that the sidewall can round off the step and guarantee that the second polysilicon can be etched completely. Experimental results show that the breakdown voltage of HV-NMOS and HV-PMOS is 114 V and -140 V, respectively; the level shifter circuit can transfer low-voltage signal(0 V/spl sim/5 V) to high-voltage signal(0 V/spl sim/95 V).

TDDI (Touch and Display Driver Integration) is a device that integrates two functions into one device. One function is as display driver IC and a second function is as a touch screen controller. For scaling to larger screen sizes for automotive applications with a TDDI architecture, multiple TDDI chips are needed due to the fan out of the required signals for supporting the display and integrated touch screen. However, in the case of TDDI multi‐chip architecture, synchronization among the plurality of chips becomes the key factor in order to achieve uniform picture quality and accurate touch response. For this paper we introduce techniques for synchronization for both the display and the touch function among a plurality of chips (TDDIs). In closing we have successfully achieved a cascaded TDDI architecture by this technique for a fully integrated automotive display and touch solution.

Display driver ICs traditionally feature high I/O counts to drive the many signals required for a high-resolution display. If LEDs are placed in a crosspoint matrix the driver IC only needs to drive the rows and the columns. But the recent advent of high-resolution micro-LEDs for adaptive automotive headlighting poses a new test challenge. The micro-LED chip is bonded on top of the silicon driver IC making connection via 20,000 I/Os, one per pixel. The driver IC becomes a backplane to the micro-LED array. Due to the I/O pitch of just <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$40\mu \mathrm{m}$</tex> and the sheer number of I/Os traditional probe card technologies become unviable. The paper describes a DfT concept that allows a self-test of the device on ATE, eliminating the need for any probing of the LED driver I/Os. Furthermore it delivers the necessary test infra-structure to prove the successful bonding between the driver IC and the micro-LED chip, allowing exact localization of assembly faults. During the mission life of the component the same DfT structures are used to monitor the health status of the headlight pixels, enabling the functional safety concept of the headlight system.

Display Driver IC is used to operate the display panel of mobile devices, such as handheld smartphones and tablets. Low power consumption becomes very important in mobile segments, thus High-k (HK)/ metal-gate (MG) process was used to fabricate DDI products. In this paper, an abnormal leakage increase observed during HTOL will be discussed along with the physical mechanism and superb HTOL results after process fixes have been implemented. As result, final DDI product showed an excellent reliability results through 1500hrs of HTOL exceeding product end of life (EOL).

The present paper describes the development of high voltage CMOS process line-up (5/11/20/30V) for display driver applications, based on 0.13mum CMOS process with aluminum metallization. The advantages are smaller size of SRAM bit cell and lower process cost. High voltage CMOS devices, 1.5V(LV) logic CMOS, 5.5V(MV)CMOS, poly-Si resistor (HR/MR), MOS-capacitor, SRAM and OTP are available. 10.8mum device pitch of 30V CMOS and good electric characteristics were successfully achieved. Thanks to the low cost and wide voltage options, various kind of display driver ICs can now be realized in smaller die size and lower cost

A display driver IC based on a current-sink driving scheme has been developed for QVGA (240times320), low-temperature poly-silicon (LTPS) active matrix organic light-emitting diodes (AMOLEDs) displays. The current-mode driver IC consists of a source driver block and a controller block. It uses a sample-and-hold scheme in the source driver block. The source driver block has 720 channel outputs, an 8-bit segmented DAC, a pre-charge generation block, and a 64-level gray scale (64 selections out of 256 gray levels for Gamma correction) per channel. The source driver output current ranges from 10 nA to 10 mum. The controller block generates control signals for the source driver and LTPS drivers (emission and scan driver), which are integrated on the panel glass. The current-mode driver IC was fabricated in a 0.18-mum CMOS technology (two poly and four metals) with 5.3-V high-voltage transistor devices

A display driver IC prototype for mobile full‐HD AMOLED display is presented. Since full‐HD AMOLED display has too short driving time, conventional R‐string DAC column driver cannot obtain enough internal settling time. To solve the problem, therefore, a new R‐string DAC column driver architecture is proposed, which has much faster settling time with high accuracy. Also, with the architecture, one 8‐bit PTL in conventional R‐string DAC is replaced with much smaller two sub‐PTLs, decreasing the overall driver area. The measured INL and DNL are 0.49 LSB and 0.38 LSB, respectively. The mean and maximum value of inter‐channel DVO is 4.6mV and 7mV, respectively. The proposed linear 10‐bit DAC fabricated on 90‐nm CMOS process occupies 81% of conventional nonlinear 8‐bit R‐string DAC area in the same technology.

In this paper, two feedback schemes, pulse skip mode and linear mode, have been analyzed in build-in-capacitor Dickson charge pumps for moderate current drivability. It is proved that the linear mode regulator has its speed constraint in high-frequency operations, where the pulse skip mode one wins. This paper takes Dickson charge pump with less than 400 μA load as an example. When a simple pulse skip control was used, only 8 μA current was consumed and the output ripples of smaller than 10 mV were obtained for all the load conditions and for a wide input-voltage range.

We report on a low cost, secure 2T-SONOS embedded nonvolatile memory (eNVM) using a novel contamination free process integration. The proposed 2T-SONOS cell utilizes reverse read method resulting in wide threshold voltage ( $\boldsymbol{V_{T}}$ ) window read margin. Using an eNVM on a 90 nm high voltage CMOS process, touch screen controller (TSC) embedded display driver IC application as well as wide input range TSC is possible. Unit cell shows 6 volt program and erase $\boldsymbol{V_{T}}$ window. However, 32 kB IP shows lower $\boldsymbol{V_{T}}$ window of 2 V due to cell $\boldsymbol{V_{T}}$ distribution, source side resistance and program disturb effect during programming. In case of programmed cells, both fresh and 1 k program/erase (P/E) cycled cells show abrupt initial $\boldsymbol{V_{T}}$ shift of 0.5 V after 48 hours of 120 °C bake test. However, erase $\boldsymbol{V_{T}}$ shift happened only at 1 k P/E cycled cell. Regardless of cycling and program/erase states, after 48 hours of bake, $\boldsymbol{V_{T}}$ shift was saturated. Thanks to the charge trap layer contamination suppressing novel process integration and optimized charge distribution, 120 °C data retention lifetime of over 10 years after 1k P/E cycling is obtained without using any special band gap engineered materials.

The effects of annealing temperature and thermal cycle conditions on the adhesion characteristics of non-cyanide Si/sputter TiW/sputter Au/Au bump structure were systematically investigated using a shear test. No intermetallic compound was observed at the TiW/Au interface at all annealing temperatures, and voids formed between the TiW and Au bump interface at a temperature higher than 280 &lt;sup&gt;o&lt;/sup&gt;C. In addition, the Au grains in the non-annealed and 250 &lt;sup&gt;o&lt;/sup&gt;C specimens formed columnar grains, while equiaxed grains formed at temperatures higher than 280 &lt;sup&gt;o&lt;/sup&gt;C. The measured shear strength of the non-annealed specimen was 44.58±3.60 MPa and it increased to 127.48±3.76 MPa at 250 &lt;sup&gt;o&lt;/sup&gt;C. However, the shear strength decreased to 101.27±3.95 MPa at 280 &lt;sup&gt;o&lt;/sup&gt;C and remained constant until 320 &lt;sup&gt;o&lt;/sup&gt;C. The toughness also dramatically increased at 250 &lt;sup&gt;o&lt;/sup&gt;C, then decreased at 280 &lt;sup&gt;o&lt;/sup&gt;C, and remained constant until 320 &lt;sup&gt;o&lt;/sup&gt;C. It is believed that the shear strength and toughness were increased because the inter-diffusion of the Au bump and the sputtered Au at 250 °C led to the formation of a single layer, causing delamination within the Au bump. However, the decrease in shear strength and toughness during annealing at 280 &lt;sup&gt;o&lt;/sup&gt;C is believed to be due to the formation of voids between the sputtered TiW and Au bump, leading to delamination at the sputtered TiW/Au bump interface. Additionally, the shear strength of the specimen annealed at 250 °C was observed to remain at approximately 100 MPa even after 1000 cycles in the thermal cycling test, which is believed to be due to the absence of changes in the Au-grain structure.

We propose a testable design method of level shifters inside a liquid crystal display driver IC. The design method enables us to detect open defects in level shifters by supply current testing that are difficult to be tested by voltage testing. Also, we show by circuit simulation that more resistive open defects may be detected by supply current testing than voltage testing, if the level shifter is designed by using the proposed DFT method.

After PLR(product level reliability) HTOL(high temperature operating lifetime) test of HV PMOSFET, Vth (threshold voltage) shift is observed to increase due to PMOSFET leakage current, which is caused by Hot Electron Induced Punch Through(HEIP). Generally, LCD display driver IC requires high voltage of more than 10V and adopts MTI(middle trench isolation) scheme which is deeply trenched to get isolation characteristics on the high voltage according to chip shrinkage. It was found that electron trapping at interface between sidewall oxide and nitride liner in middle trench isolation(MTI) induces channel shorting at the corner of transistor, thereby resulting in the leakage current. In this paper, we propose the optimized sidewall thickness and the effectiveness of additional annealing process which have strong resistance against hot electron induced punch through regarding that offset leakage current is increased after HTOL(high temperature operating lifetime) stressing test for devices prepared with MTI processing scheme and it might be improved by the optimization of sidewall oxide thickness. Therefore, the threshold voltage(Vth) shift is seriously reduced due to the increase of immunity on the hot electron induced punch-through(HEIP) according to the increase of the sidewall thickness and adding annealing process as the thermal oxide layer of high temperature.

We report herein on the first commercial production of 32V high voltage Field-Drift MOSFET (FDMOS) embedded in HK/MG with RMG technology. To overcome the challenges encountered during the RMG process, a recessed structure with a specifically designed poly gate patterning was developed. By using the new scheme, the devices can prevent metal gate disruptions. By comparison with the traditional devices in poly/SiON technology, the recessed devices can maintain good performance without degradation. Some extra benefits are obtained with the scheme by 4 V improvement of gate dielectric breakdown. This approach can provide technological mass production techniques and reliable device characteristics for future PMIC and display driver ICs applications.