16 nm FinFET Based Radiation Hardened Standard Cell Library Analysis Using Visual TCAD Tool

Measurement and evaluation of the Single Event Effects of high-performance SerDes circuits

A key point in SEE (Single Event Effect) simulation experiment is how to calculate the equivalent LET (Linear Energy Transfer) for laser pulse. In this paper, the calculation method considering the influences of nonlinear absorption in semiconductor, reflection and refraction on device surface and other factors is presented. Simultaneously an instance of calculation is provided, with the result in good agreement with the SEU (Single Event Upset) threshold measured by heavy ions.

Due to the advances in electronics design automation industry, worldwide, the integrated approach to model and emulate the single event effects due to cosmic radiation, in particular single event upsets or single event transients is gaining momentum. As of now, no integrated methodology to inject the fault in parallel to functional test vectors or to estimate the effects of radiation for a selected function in system on chip at design phase exists. In this paper, a framework, PRogrammable single Event effects Demonstrator for dIgital Chip Technologies (PREDICT) failure assessment for radiation effects is developed using a hardware platform and aided by genetic algorithms addressing all the above challenges. A case study is carried out to evaluate the frameworks capability to emulate the effects of radiation using the co-processor as design under test (DUT) function. Using the ML605 and Virtex-6 evaluation board for single and three particle simulations with the layered atmospheric conditions, the proposed framework consumes approximately 100 min and 300 min, respectively; it consumes 600 min for 3 particle random atmospheric conditions, using the 64 GB RAM, 64-bit operating system with 3.1 GHz processor based workstation. The framework output transforms the 4 MeVcm2/mg linear energy transfer to a single event transient pulse width of 2 μs with 105 amplification factor for visualisation, which matches well with the existing experimental results data. Using the framework, the effects of radiation for the co-processing module are estimated during the design phase and the success rate of the DUT is found to be 48 per cent.

Single-event effects (SEEs) have been the primary concern in study of radiation effects since late 1970s with the discovery of soft errors in terrestrial and space environments. The interaction of a single ionized particle with electronic devices leads to SEEs. In this paper, single-event upset (SEU) on CMOS devices in designing of a voltage-controlled oscillator (VCO) is analysed. Further, mitigation approaches of SEU are also discussed. To observe the impact of radiation, a VCO was designed in Cadence Virtuoso, and GDSII file of one ring oscillator stage was extracted to incorporate the same design in Silvaco MaskViews. With the help of layer map information file, masks were identified and used to design the CMOS inverter structure file for simulation of SEU condition. The input parameters for SEU simulation were evaluated from linear energy transfer (LET) graph of heavy ion under space conditions. The current profile of CMOS inverter was extracted under influence of a high-energy particle with the help of LET graph of that particle. This current profile was applied to different nodes of VCO and upset conditions were identified. Further, the impact of upset conditions on lock stage of phase-locked loop (PLL) is discussed. Results show that the SEU has significant impact on the logic state of inverters used in ring oscillator stage compared with current starving/biasing stage. The current profile of CMOS device has strong dependence on the energy of ion, its track, angle of incidence and the material. When angle of incidence is very less (\(7^{\circ }-14^{\circ }\)) the channel will be occupied by a funnel of charge and it leads to the maximum degradation of device. This work shows that a device operating at high frequency is more susceptible to SEU. Triple modular redundancy (TMR) and Radiation Hardened By Design (RHBD) can be used to mitigate SEU. TMR consumes more power and is less accurate compared with the RHBD approach.

In this paper we describe the fault injection models for the systems tolerant to the single event upsets (SEU) and single event transients (SET). The presented fault modelling approach is based on the random generated SEU faults in sequential logic and SET faults in combinational logic. The fault injection models for triple modular redundant (TMR) and dual modular redundant (DMR) circuits are developed in order to simulate the fault-tolerant systems. The analytical models for calculation of the probability of failure-free TMR and DMR circuits are defined too. To justify the reduced redundancy concept, the simulated and calculated probabilities of failure-free TMR and DMR circuits are presented and discussed. The obtained results show a better trade-off between hardware overhead and circuit failure-free probability of the DMR concept.

The dependence of 0.13µm NMOS single event transient on linear energy transfer (LET) is studied and integrated into a single event transient (SET) pulses fault injection model. A modified double exponential function with four parameters that are related to LET is used to fit the single event transient pulsed current. By translating into the LET-dependent model, it can predict the charge collection without Technology Computer Aided Design (TCAD) simulation when LET is changed. The SRAM unit is built using the proposed single event transient pulses fault injection model into the sensitive node, proving the practicability and reasonableness of the proposed fault injection model for circuit-level single-event effect (SEE) simulation.

During a solar particle event (SPE) a spacecraft can suffer a large number of single event effect (SEE) anomalies due to the enhanced energetic ion environment. Throughout satellite design, simulations can be made to estimate the mission single event upset (SEU) rate. One of the most used models to predict in-orbit SEU rate is cosmic ray effects on microelectronics (CREME96). CREME96 treats solar particle events on the basis of a specific event-October 1989. Some engineering applications require evaluation of expected SEU behavior in a range of SPE types. In addition, comparison cannot be made directly between in-flight SEU behavior during SPEs and the CREME96 prediction. To address these issues, we examine the feasibility of using available environmental datasets to derive linear energy transfer (LET) spectra. We find serious problems with many datasets, particularly with availability of data during the most significant SPEs. It is also difficult to derive data on SEU behavior of systems. Where comparisons are possible, we find that shielding plays a significant role. Again, obtaining shielding data concerning a part proves difficult. Recommendations are made with respect to environmental data sources, analysis methods and engineering procedures to safeguard lessons learned type exercises/comparison of prediction. Three different SPEs [November 6, 1997, July 14, 2000, and November 9, 2000] have been evaluated. As target device, The Solar and Heliospheric Observatory solid state recorder is analyzed.

High-energy particles in space often induce single event effects in CMOS image sensors, resulting in performance degradation and functional failure. This paper focuses on the formation and morphology of transient bright spots in CMOS image sensors and analyzes the formation process of transient bright spots by conducting heavy ion irradiation experiments to obtain the variation law of transient bright spots with heavy ion linear energy transfer values and background gray values; in addition, we classify the single event upset that occurred in the experiments according to the state of transient bright spots and extract the characteristics of different single event upsets. The failure mechanisms of different single event upsets are analyzed according to their characteristics and are combined with the information given by transient bright spots. This provides an essential reference for rapidly evaluating single event effects and the reinforcement design of CMOS image sensors.

Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage cells or by sampling single event transients (SETs) from a logic path. An accurate prediction of soft error susceptibility from SETs requires good models to convert collected charge into compact descriptions of the current injection process. This paper describes a simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations. The model uses two double-exponential current sources in parallel, and the results illustrate why a conventional model based on one double-exponential source can be incomplete. A small set of logic cells with varying input conditions, drive strength, and output loading are simulated to extract the parameters for the dual double-exponential current sources. The parameters are based upon both the node capacitance and the restoring current (i.e., drive strength) of the logic cell.

Microprocessor-based system's robustness under Single Event Effects is a very current concern. A widely adopted solution to make robust a microprocessor-based system consists in modifying the software application by adding redundancy and fault detection capabilities. The efficiency of the selected software-based solution must be assessed. This evaluation process allows the designers to choose the more suitable robustness technique and check if the hardened system achieves the expected dependability levels. Several approaches with this purpose can be found in the literature, but their efficiency is limited in terms of the number of faults that can be injected, as well as the level of accuracy of the fault injection process. In this paper, we propose FPGA-based fault injection techniques to evaluate software robustness methods under Single Event Upset (SEU) as well as Single Event Transient (SET). Experimental results illustrate the benefits of using the proposed fault injection method, which is able to evaluate a high amount of faults of both types of events.

The impacts of the gate length and width of the transistors on the single event upset (SEU) hardness of static random access memory (SRAM) cells has been investigated by SPICE simulations, biased on a partially depleted (PD) silicon-on-insulator (SOI) CMOS technology. The results show that increasing the gate width can dramatically enhance the linear energy transfer (LET) threshold of SEU, as compared with increasing the gate length. A new parameter, unit gate area LET threshold, is introduced for characterizing the change in efficiency of improving the SEU resistance with increasing the gate length and width of the transistors in a cell. The effect of decoupling capacitors on cell SEU LET threshold is also presented by making a comparison with that of the transistors with increased gate lengths.

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations

Single event upset mitigation by means of a sequential circuit state freeze

Strong fields of bremsstrahlung photons and photoneutrons are produced during the operation of high-energy electron linacs. Therefore, a mixed gamma and neutron radiation field dominates the accelerators environment. The gamma radiation induced Total Ionizing Dose (TID) effect manifests the long-term deterioration of the electronic devices operating in accelerator environment. On the other hand, the neutron radiation is responsible for Single Event Effects (SEE) and may cause a temporal loss of functionality of electronic systems. This phenomenon is known as Single Event Upset (SEU). The neutron dose (KERMA) was used to scale the neutron induced SEU in the SRAM chips. Hence, in order to estimate the neutron KERMA conversion factor for Silicon (Si), dedicated calibration experiments using an Americium-Beryllium ( 241 Am/Be) neutron standard source was carried out. Single Event Upset (SEU) influences the short-term operation of SRAM compared to the gamma induced TID effect. We are at present investigating the feasibility of a SRAM based real-time beam-loss monitor for high-energy accelerators utilizing the SEU caused by fast neutrons. This paper highlights the effects of gamma and neutron radiations on Static Random Access Memory (SRAM), placed at selected locations near the Superconducting Linear Accelerator driving the Vacuum UV Free Electron Laser (VUVFEL) of DESY.

The single event effect (SEE) and the total ionizing dose (TID) effect of a commercial enhancement mode gallium nitride (GaN) high electron nobility transistor (HEMT) with p-type gate structure and cascode structure are studied by using the radiation of heavy ions and <sup>60</sup>Co gamma in this paper. The safe operating areas ofSEE, the sensitive parameters degradation of TID effect and the SEE and TID characteristics of GaN HEMT device are respectively presented. The experimental results show that the SEE and TID effect have less influence on the p-type gate GaN device. The linear energy transfer (LET) threshold of the single event Burnout effect (SEB) is higher than 37 MeV·cm<sup>2</sup>/mg and the failure threshold of TID effect is above 1M rad (Si) for p-type gate GaN device. However, the GaN HEMT device with cascode structure is much more sensitive to SEE and TID effect than p-type gate GaN device. Under heavy ions at LET of 22 MeV·cm<sup>2</sup>/mg and a cumulative dose of 200 krad (Si), the SEB phenomenon and parameters-degradation of cascode-type GaN HEMT are respectively observed. Besides, the circuit structure of the cascode-type GaN HEMT device is analyzed by using metallographic microscope imaging and focused ions beam technology. It reveals the possible reason why it is sensitive to SEB and TID for cascode-type GaN HEMT. These results show that the extra carriers caused by heavy ion radiation can tunnel the Schottky barrier formed by gate metal and AlGaN layer, leading to a large source-drain current in GaN HEMT device. Meanwhile, it is shown that the metal oxide semiconductor field-effect transistor in cascode circuit for TP90H180PS GaN HEMT may be the main reason why the cascode-type GaN HEMT is sensitive to TID.