Modeling of Single Event Transients With Dual Double-Exponential Current Sources: Implications for Logic Cell Characterization

The proposed work analyzes the Single Event Transients (SETs) in combinational circuits and Single Event Upsets (SEUs) in sequential elements for 16 nm FinFET device structures implemented using Visual TCAD tool. The FinFET CMOS circuits of traditional and Dual-port Radhard designs are compared for power consumption and particle strike immunity. As the radhard circuits are inherently redundant this causes proportional increase in power consumption which is ~2 times as compared to traditional design. In the presented work, the radiation resilience of the implemented radhard circuits, measured in terms of critical charge (QC), has drastically improved by greater than three order as compared to the traditional designs. With this improvement the radhard designs can in turn withstand an accelerated heavy ion particle strike with Linear Energy Transfer (LET) up to 50 MeV-cm2/μm for SETs and LETs upto 100 MeV-cm2/μm for SEUs. Finally, the Visual TCAD particle strike simulation showed that the radhard FinFET circuits were resilient and adjacent nodes were not affected for increased energy levels.KeywordsFinFETsRadiation hardeningStandard cellTotal Ionizing Dose (TID)Single Event Effects (SEEs)Single Event Upsets (SEUs)LET

Due to the advances in electronics design automation industry, worldwide, the integrated approach to model and emulate the single event effects due to cosmic radiation, in particular single event upsets or single event transients is gaining momentum. As of now, no integrated methodology to inject the fault in parallel to functional test vectors or to estimate the effects of radiation for a selected function in system on chip at design phase exists. In this paper, a framework, PRogrammable single Event effects Demonstrator for dIgital Chip Technologies (PREDICT) failure assessment for radiation effects is developed using a hardware platform and aided by genetic algorithms addressing all the above challenges. A case study is carried out to evaluate the frameworks capability to emulate the effects of radiation using the co-processor as design under test (DUT) function. Using the ML605 and Virtex-6 evaluation board for single and three particle simulations with the layered atmospheric conditions, the proposed framework consumes approximately 100 min and 300 min, respectively; it consumes 600 min for 3 particle random atmospheric conditions, using the 64 GB RAM, 64-bit operating system with 3.1 GHz processor based workstation. The framework output transforms the 4 MeVcm2/mg linear energy transfer to a single event transient pulse width of 2 μs with 105 amplification factor for visualisation, which matches well with the existing experimental results data. Using the framework, the effects of radiation for the co-processing module are estimated during the design phase and the success rate of the DUT is found to be 48 per cent.

Microprocessor-based system's robustness under Single Event Effects is a very current concern. A widely adopted solution to make robust a microprocessor-based system consists in modifying the software application by adding redundancy and fault detection capabilities. The efficiency of the selected software-based solution must be assessed. This evaluation process allows the designers to choose the more suitable robustness technique and check if the hardened system achieves the expected dependability levels. Several approaches with this purpose can be found in the literature, but their efficiency is limited in terms of the number of faults that can be injected, as well as the level of accuracy of the fault injection process. In this paper, we propose FPGA-based fault injection techniques to evaluate software robustness methods under Single Event Upset (SEU) as well as Single Event Transient (SET). Experimental results illustrate the benefits of using the proposed fault injection method, which is able to evaluate a high amount of faults of both types of events.

Single event upset mitigation by means of a sequential circuit state freeze

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations

In this paper we describe the fault injection models for the systems tolerant to the single event upsets (SEU) and single event transients (SET). The presented fault modelling approach is based on the random generated SEU faults in sequential logic and SET faults in combinational logic. The fault injection models for triple modular redundant (TMR) and dual modular redundant (DMR) circuits are developed in order to simulate the fault-tolerant systems. The analytical models for calculation of the probability of failure-free TMR and DMR circuits are defined too. To justify the reduced redundancy concept, the simulated and calculated probabilities of failure-free TMR and DMR circuits are presented and discussed. The obtained results show a better trade-off between hardware overhead and circuit failure-free probability of the DMR concept.

A single event transient (SET) filtering technique for non-volatile field programmable gate arrays (FPGAs) are investigated experimentally using the AND-OR-Multiplexer SET filter technique. The technique combines AND – OR gate circuits in parallel with a two input multiplexer to provide a single circuit that can dissipate SETs irrespective of whether the input state is high or low. This paper presents the results of the experimental investigation, with the SET filter applied to various sequential circuit configurations in a commercial Flash-based FPGA, the 0.13-μm ProASIC3E product family (A3PE), by proton beam irradiation. Their implementation and evaluation in-beam show their efficiency in eliminating SETs and single event upsets (SEU) compared to unmitigated designs.

High-energy particles in space often induce single event effects in CMOS image sensors, resulting in performance degradation and functional failure. This paper focuses on the formation and morphology of transient bright spots in CMOS image sensors and analyzes the formation process of transient bright spots by conducting heavy ion irradiation experiments to obtain the variation law of transient bright spots with heavy ion linear energy transfer values and background gray values; in addition, we classify the single event upset that occurred in the experiments according to the state of transient bright spots and extract the characteristics of different single event upsets. The failure mechanisms of different single event upsets are analyzed according to their characteristics and are combined with the information given by transient bright spots. This provides an essential reference for rapidly evaluating single event effects and the reinforcement design of CMOS image sensors.

Strong fields of bremsstrahlung photons and photoneutrons are produced during the operation of high-energy electron linacs. Therefore, a mixed gamma and neutron radiation field dominates the accelerators environment. The gamma radiation induced Total Ionizing Dose (TID) effect manifests the long-term deterioration of the electronic devices operating in accelerator environment. On the other hand, the neutron radiation is responsible for Single Event Effects (SEE) and may cause a temporal loss of functionality of electronic systems. This phenomenon is known as Single Event Upset (SEU). The neutron dose (KERMA) was used to scale the neutron induced SEU in the SRAM chips. Hence, in order to estimate the neutron KERMA conversion factor for Silicon (Si), dedicated calibration experiments using an Americium-Beryllium ( 241 Am/Be) neutron standard source was carried out. Single Event Upset (SEU) influences the short-term operation of SRAM compared to the gamma induced TID effect. We are at present investigating the feasibility of a SRAM based real-time beam-loss monitor for high-energy accelerators utilizing the SEU caused by fast neutrons. This paper highlights the effects of gamma and neutron radiations on Static Random Access Memory (SRAM), placed at selected locations near the Superconducting Linear Accelerator driving the Vacuum UV Free Electron Laser (VUVFEL) of DESY.

PurposeThe purpose of this paper is to present a transition detector (TD)-based radiation hardened flip-flop (TDRH-FF) for single event upset (SEU).Design/methodology/approachWith SEU recovery and single event transient (SET) detector mechanism, the TDRH-FF can tolerate SEU during hold mode and generate a warning signal for architecture-level recovery during transport mode when input signal contains SET. Evaluation results show that the TDRH-FF outperforms comparable comprehensive performance.FindingsSimulation results show that 1) the mean pulse width of the correction glitches (at full width half maximum) of TDRH-FF is less than 10 ps; 2) the area overhead of TDRH-FF is similar to the EVFERST-FF, BISER-FF and DNURHL-FF; 3) TDRH-FF has the same average power consumption as SETTOF, and moderate PDP and Ps values among these compared FFs.Originality/valueIn this paper, a TD-based TDRH-FF is proposed to solve the problems in the previous design. And the main contributions of the proposed TDRH-FF are summarized: Minimum size transistors are used in the proposed TD which leads to a considerable decrease in area overheads and propagation delay (resulting in an ignorable correction glitch); and compared with other radiation hardened flip-flop, TDRH-FF outperforms comparable comprehensive performance.

Measurement and evaluation of the Single Event Effects of high-performance SerDes circuits

This paper proposes soft error immune flip-flop (SEIFF) for mitigating single event upset (SEU) in flip-flops (FFs) and impact of single event transient (SET) in combinational-logic. SEIFF mitigates the SET without enlarging setup-time and delay; there is no overhead in circuit performance. Alpha and proton tests validate the mitigation efficiency in SEIFF manufactured on 10 nm FinFET technology.

Dual-Interlocked-Cell (DICE) latches are tolerant to Single Event Effects (SEE) by design owing to intrinsic redundancy. In nanometric technologies, as in the 65 nm scale, there are new SEE vulnerabilities associated with charge sharing between nodes. Herein we present a systematic analysis of the robustness against radiation using a simulation software tool for analog and mixed-signal circuits (AFTU) that emulates the possible effects generated by particle impacts. In this paper, we evaluate the influence of SEE on circuit performance using this tool as an RHbD assessment for designers. An exhaustive study of the possible vulnerabilities of the DICE architecture is performed, including an evaluation of the proximity between critical nodes at the layout level. As a result, we propose several modifications to the cell implementation to optimize its robustness against Single Event Upsets (SEU). An assortment of five designs with different variations of the original DICE scheme was sent for fabrication on a new chip and tested under ion beams, with promising results showing a clear improvement in the SEU sensitivity of the cell. The best results come from a redesign of the load circuitry to avoid a SET2SEU effect and full interleaved layout to avoid charge sharing effects after a single event.

In the context of implementing more control and data processing capabilities in new electronic cards at the European Organization for Nuclear Research (CERN), the Smartfusion2 Flash-based Reprogrammable Field Programmable Gate Array (FPGA) has been tested in the CHARM radiation facility at CERN. The CHARM facility was configured to offer a representative radiation environment of the CERN's Large Hardon Collider (LHC) accelerator. The FPGAs were tested during three irradiation campaigns. The observed radiation effects include Single Event Upsets (SEU), Single Event Transients (SET), Single Event Latch-ups (SEL), Single Event Functional Interrupts (SEFI) and failures due to Total Ionizing Radiation (TID). The use of this FPGA is linked to the implementation of appropriate Finite State Machine (FSM) encoding, Printed Circuit Board (PCB) design, and automated power cycling that are here discussed. The suitability of the FPGA in harsh environments and critical applications such as the cryogenics electronics infrastructure in the LHC tunnel is also discussed.

Some single event upset (SEU)-hardened flip-flops cannot mitigate single event transients (SET) that come from the upstream combinational circuits and propagate to the data inputs of flip-flops near the capturing clock edge. This paper presents a SET suppressor that can mitigate such SETs. By adjusting the clock edge timing so that the flip-flop captures data when the data returns to a correct state, the SET suppressor protects a flip-flop against SETs. The clock edge timing adjustment results in flip-flop delay. However, the SET suppressor almost does not introduce flip-flop delay when no SET occurs near the capturing clock edge, which is a great majority of time.