32nm design rule and process exploration flow

Considering Part Orientation in Design for Additive Manufacturing

Voltage flicker of PV plants due to the illumination condition is widely discussed. This paper introduced a flicker assessment method for PV plants considering the illumination variation. By wavelet transform method, the illumination condition is classified into four typical type. The PV inverter is tested under these typical condition and the PV station model are built on simulation platform. Then the flicker of PCC under typical condition is simulated. Using wavelet transform and statically method, weights of four typical type is calculated from the illumination condition historical data. By the simulation results and weights of four illumination condition, the flicker assessment considering an area's illumination condition is given. In this paper, the evaluation model and the evaluation process of the PV station are of a certain reference value for the evaluation of photovoltaic power station.

As reticle enhancement techniques (OPC, PSM) become more commonly used in multi-masking levels for 130nm node and below, the need for a better and more precise reticle specification will be even greater. OPC and sub-nominal assist feature like scattering bar represent a challenge for mask metrology tools. Consequentiy, defect inspection for advanced reticles has become a gating step for both Mask shops and Wafer Fabs alike. In this paper, a binary defect test reticle with and without OPC/SB features, manufactured by Dupont Photomask’s Reticle Technology Center, was used for the study. The reticle was made using the ALTA 3500 Laser Writer Tool and dry chrome etch process. Reticle inspection results from KLA363UV for 0. 13 um design rule patterns in both Clear and Dark polarities, with bump, divot and pinhole programmed defects between 0.1 and 0.6 um sizes (at 4x) were shown. These results were then compared to the wafer printability using ArF 193nm lithography. The impact of each defect type on 0.13 um Isolated, Semi-Dense and Dense lines was evaluated for 10% CD tolerance to provide an assessment on the KLA363UV inspection tool capability. A set of edge defects (bump and divot) and point defect (hole between line ends) from 0.1 to 0.6 um on the reticle (4x) were repaired using the Seiko SIR-3xxx tool at DPI-RTC. The printability of repairs on wafer at 193nm exposure wavelength was evaluated. CD of repaired features was compared to that of nominal feature for both reticle and resist wafer to evaluate the repair effectiveness. Finally, a defect specification for 0.13 um design rule binary reticle using ArF lithography is discussed.

Machine vision systems are applied in industry to control the quality of production while optimizing efficiency. A machine vision and AI-based inspection of color intensity in transparent Polyethylene Terephthalate (PET) preforms is especially sensitive to backgrounds and lighting, therefore, much attention is given to its illumination conditions. The paper examines the adverse factors affecting the quality of image recognition and presents an adaptive method for reducing the influence of changing illumination conditions in the color inspection process of transparent PET preforms. The method is based on predicting measured color intensity correction parameters according to illumination conditions. To test this adaptive method, a hardware and software system for image capture and processing was developed. This system is capable of inspecting large quantities of preforms in real time using a neural network with a modified gradient descent and momentum algorithm. The experiment showed that correction of the measured color intensity value reduced the standard deviation caused by variable and uneven illumination by 61.51 & x0025;, demonstrating that machine vision color intensity evaluation is a robust and adaptive solution under illuminated conditions for detecting abnormalities in machine-based PET inspection procedures.

The 22-nm technology node presents a real breakthrough compared to previous nodes in the way that state of the art scanner will be limited to a numerical aperture of 1.35. Thus we cannot simply apply a shrink factor from the previous node, and tradeoffs have to be found between Design Rules, Process integration and RET solutions in order to maintain the 50% density gain imposed by the Moore's law. One of the most challenging parts to enable the node is the ability to pattern Back-End Holes and Metal layers with sufficient process window. It is clearly established that early process for these layers will be performed by double patterning technique coupled with advanced OPC solutions. In this paper we propose a cross comparison between possible double patterning solutions: Pitch Splitting (PS) and Sidewall Image Transfer (SIT) and their implication on design rules and CD Uniformity. Advanced OPC solutions such as Model Based SRAF and Source Mask Optimization will also be investigated in order to ensure good process control. This work is a part of the Solid's JDP between ST, ASML and Brion in the framework of Nano2012 sponsored by the French government.

The practical issues of i-line lithography process development and design rule considerations for 0.4-0.35 /spl mu/m DRAM (dynamic random access memory) manufacturing were addressed in this paper. Based on published literature and our development experience in 64 Mb DRAM, a list of lithography requirements for DRAM manufacturing was proposed and discussed. The details on focus budget issue were discussed also. A tremendous DOF (depth of focus) loss on the critical layer processes occurred without the considerations of local and global proximity effects and metrology errors on 0.4 /spl mu/m and below processes. Combining an optical proximity correction (OPC) technique with design rule modifications, a factor of 2-3 improvement in UDOF (usable DOF) was proven. Thinner resist thickness and mask quality control which become inevitable for the coming generations were discussed also.

BackgroundThe advancements in unmanned aerial vehicle (UAV) technology have recently emerged as an effective, cost-efficient, and versatile solution for monitoring crop growth with high spatial and temporal precision. This monitoring is usually achieved through the computation of vegetation indices (VIs) from agricultural lands. The VIs are based on the incoming radiance to the camera, which is affected when there is a change in the scene illumination. Such a change will cause a change in the VIs and subsequent measures, e.g., the VI-based chlorophyll-content estimation. In an ideal situation, the results from VIs should be free from the impact of scene illumination and should reflect the true state of the crop’s condition. In this paper, we evaluate the performance of various VIs computed on images taken under sunny, overcast and partially cloudy days. To improve the invariance to the scene illumination, we furthermore evaluated the use of the empirical line method (ELM), which calibrates the drone images using reference panels, and the multi-scale Retinex algorithm, which performs an online calibration based on color constancy. For the assessment, we used the VIs to predict leaf chlorophyll content, which we then compared to field measurements.ResultsThe results show that the ELM worked well when the imaging conditions during the flight were stable but its performance degraded under variable illumination on a partially cloudy day. For leaf chlorophyll content estimation, The r^2 of the multivariant linear model built by VIs were 0.6 and 0.56 for sunny and overcast illumination conditions, respectively. The performance of the ELM-corrected model maintained stability and increased repeatability compared to non-corrected data. The Retinex algorithm effectively dealt with the variable illumination, outperforming the other methods in the estimation of chlorophyll content. The r^2 of the multivariable linear model based on illumination-corrected consistent VIs was 0.61 under the variable illumination condition.ConclusionsOur work indicated the significance of illumination correction in improving the performance of VIs and VI-based estimation of chlorophyll content, particularly in the presence of fluctuating illumination conditions.

Design shrinking beyond the resolution limits of 193 nm optical lithography requires the introduction of double patterning technology (DPT) for the semiconductor industry. Two consecutive lithography and etching process (LELE; Litho-Etch-Litho-Etch) and self aligned double patterning (SADP) process are major two options of DPT.In LELE process, layout patterns are decomposed into two groups and each group is placed on a photo mask. The original layout is reconstructed on a wafer through two lithography with two those photo masks. The two lithography processes are independent because of the intermediate process in between, such as etching and resist freeze. Lithography conditions for each mask are optimized on source mask optimization (SMO) technique to enlarge lithography margin. Conventional SMO technique can be applied to the decomposed patterns since two lithography processes have no interaction as discussed above.In SADP process, a layout is also decomposed into two groups as same as the methodology for LELE process. Either decomposed group is transferred on a wafer, which is named as mandrel. Sidewalls are deposited on the mandrel patterns and the following processes such as etching and mandrel removal reconstruct the original layout.Design rules for DPT consist of two parts. One is for an original layout which is drawn by designers. The other is for each decomposed layout printed by a lithography process. Both design rules have interactions because the original layout which follows the former design rules is decomposed into two groups which follow the latter design rules.In this paper, we will discuss the relation between the two rules above. Furthermore, we will discuss the situation on triple or quadruple patterning.

A reduction efficiency of shot numbers in character projection (CP) electron-beam (EB) lithography with memory device application depends on a design rule (cell size) and a pattern complexity within a memory cell. Many researchers reported that it was approximately 1/10 to 1/100 compared with conventional variable-shaped beam (VSB) method. The reduction of shot numbers in memory devices mainly comes from allowance to place multiple cells in one CP-cell area and simplicity of the cell's placement (regular pitch with adjacent allocation). On the other hand, there are few reports concerning reduction efficiency of shot numbers with logic specific application in CP EB lithography due to the complexity of logic cell's allocation to CP-cell area. To analyze this, logic device layout data in 70nm node was prepared by shringking actual functional device data of 350 nm node in the ratio of 1/5 and extracting random logic region. The size of this region was 1,094 x 283 micrometers . The height of logic cell was 2.64micrometers and it was smaller than typical one CP-cell size in second aperture (5 x 5micrometers ). The pattern data in GDS-II stream format was converted into EB exposure data: divided figures (rectangles). By this procedure, numbers of figures and cells were obtained. The total number of referred logic cell was 26,812. Among 26,812 cells, only 111 common (unique) logic cells were used for the logic region. The sum of figures in gate layer was 412,251 and this value was assumed to be equal to a total number of shots in conventional VSB method. Among the 111 common cells, only 6 cells in the gate layer showed width more than 5micrometers (maximum CP-cell size). Most frequently referred cell was an inverter and the number of reference was 5,395. The referred frequency of each cell exponentially decreased when the cells were arranged in descending order of reference. Among the total figures, top cell showed 66,120 accumulated number of figures (referred number=2,204, figures in cell=30). The cumulative number of total shots also exponentially decreased when cells were arranged in descending order of total shots. So it is necessary to decide the appropriate maximum number of CP- cell for futur CP EB exposure systems considering the reductoin efficiency of the shot numbers. For the current CP EB exposure tool of Hitachi (HL system), allowed number of CP-cell is 21 which means only 5 different (frequently referred) logic cells can be allocated in CP aperture with typical placement in 4 orientations. But even in this case, total required shot numbers of this logic region for EB Exposure can be reduced to approximately ½. For the ADVANEST CP EB system (allowed number of CP-cell = 100), reduction ratio of shot numbers is 1/4. For the pseudo CP EB system with 500 CP-cells in second aperture, reduction ratio of shot numbers would be 1/15. So, CP EB lithography is one of the promising candidates for small or medium volume production technology especially memory with logic device application after 70 nm node if the maximum number of CP-cell is appropriately increased.

Charging damage from plasma processing can be reduced through process architecture and plasma hardware and process optimization, but not all damage can be prevented. Antenna area ratio design rules are commonly used in the semiconductor industry to ensure that the remaining charging does not damage circuits. A procedure for defining and quantifying simple antenna design rules is shown in this paper. In a case study, poly and metal antenna area ratios of 300:1 are chosen as the design rule maximum. The limitations of these design rules are also discussed.

With the ever increasing complexity of today's IC packaging designs and new packaging technologies of tomorrow, coupled with the increasingly global nature of design and manufacturing / assembly, traditional 2-D EDA packaging tools and design collaboration capabilities do not have the required feature subsets nor controlled and seamless design sharing integration needed to support 3-D design technologies. These current solutions cannot adequately meet advanced packaging's current and future needs. New generation 3-D EDA tools and design collaboration systems that integrate 3-D design and global data collaboration are required to meet these expanding technologies. The conventional 2-D IC package design process flow begins with top-down design and layout, and utilize software tools that only have the ability to verify 2-D design rule checks (DRC). These limited rules, while sufficient for lead frame, single tier Ball Grid Array (BGA), and other single level package types, do not take into consideration advanced System in Package (SiP) stacked die configurations with multi-die advanced bond wire and other connection technologies with accompanying manufacturing variables and tolerances. The lack of tools that accurately model these 3-D manufacturing parameters result in substantial trial and error in the assembly set up process, increasingly poor yields as complexity increases, and in some cases, eventual package / substrate redesign after costly time and resources in manufacturing have already been expended. In addition, the design and manufacturing and assembly departments tend to be organizationally as well as geographically separated with little or no real data transfer or feedback between the departments. The result is evident in current package designs that are completed according to basic rules without the benefit of, nor the ability to incorporate optimal manufacturing data. These designs are completed “successfully” (from a 2-D design standpoint) and then sent to manufacturing and assembly. These “successful” designs are then evaluated from a manufacturing and assembly viewpoint, and real world manufacturing parameters are utilized to “redesign” the assembly of the package to attempt to make the package manufacturable. The optimization of the design for manufacturing can take days or weeks to accomplish through a long process of trial and error. Many iterations of the assembly prototype are made until it is deemed manufacturable, or if not, the design is sent back to the design department for re-design. In order to increase reliability, increase yields, and decrease time to market for advanced SiP and other stacked technologies, a 3-D design collaboration system is required to integrate the design, verification, manufacturing, and assembly processes into a seamless system that is globally accessible in real time by all departments. This system must provide data access to the designer from all related departments, including engineering, simulation, manufacturing, assembly, etc. in order for the designer to be able to optimize the design for maximum performance as well as the highest yield and shortest time-to-market. This system will accurately verify 3-D assembly parameters during the design process. Manufacturing, engineering, and assembly departments will be able to input manufacturing parameters into the design, thereby eliminating much of the trial and error prone in the package design and assembly process today, and the design can be shared by multiple users and departments for true collaboration. This paper explains the role and manufacturing benefits of a 3-D package design and global data collaboration system.

Optical projection lithography has been the workhorse of the integrate circuit (IC) manufacturing industry to transfer the computer‐aided design (CAD) to semiconducting material wafers. The resolution limit of the 193 nm wavelength lithography which was initially targeted for the 90 nm design rule has been further extended to realise ∼10–20 nm devices with ingenious interventions. The three‐dimensional fin‐shaped field‐effect transistor device structure now realise the <20 nm design rule still using 193 nm projection lithography as the widely accepted solution. The extreme ultraviolet wavelength source systems are still in development and testing phases with some recent success reported, but still falling short of supporting volume production requirements. This study reviews the current trends in lithography and the associated resolution enhancement techniques with brief introduction to an integrated CAD analysis for hotspot detection.

Real-world surface textures commonly consist of a spatial variation of reflectance properties combined with rough surface geometry, called 3D surface texture. Variation of illumination can produce dramatic changes their appearance. While previous work on super resolution pays great attention to 2D images, this paper proposes an inexpensive method for super resolution on 3D surface textures. First, four images under different illumination angles are captured for each sample surface texture, from which the surface gradient maps and the albedo map are extracted by Photometric Stereo. Then the surface gradient and albedo maps and three selected original images, which represent 3D surface texture, are processed by a modified 2D Example-based super resolution method to generate result representation sets with higher resolution. Finally, relight surface representations to generate high resolution texture images under any different illumination conditions. Experimental results show that this method provides more fine details compared to interpolation techniques.

A class of techniques in computer vision and graphics is based on capturing multiple images of a scene under different illumination conditions. These techniques explore variations in illumination from image to image to extract interesting information about the scene. However, their applicability to dynamic environments is limited due to the need for robust motion compensation algorithms. To overcome this issue, we propose a method to separate multiple illuminants from a single image. Given an image of a scene simultaneously illuminated by multiple light sources, our method generates individual images as if they had been illuminated by each of the light sources separately. To facilitate the illumination separation process, we encode each light source with a distinct sinusoidal pattern, strategically selected given the relative position of each light with respect to the camera, such that the observed sinusoids become independent of the scene geometry. The individual illuminants are then demultiplexed by analyzing local frequencies. We show applications of our approach in image-based relighting, photometric stereo, and multiflash imaging.

Benchmark datasets used for testing computer vision (CV) methods often contain little variation in illumination. The methods that perform well on these datasets have been observed to fail under challenging illumination conditions encountered in the real world, in particular, when the dynamic range of a scene is high. The authors present a new dataset for evaluating CV methods in challenging illumination conditions such as low light, high dynamic range, and glare. The main feature of the dataset is that each scene has been captured in all the adversarial illuminations. Moreover, each scene includes an additional reference condition with uniform illumination, which can be used to automatically generate labels for the tested CV methods. We demonstrate the usefulness of the dataset in a preliminary study by evaluating the performance of popular face detection, optical flow, and object detection methods under adversarial illumination conditions. We further assess whether the performance of these applications can be improved if a different transfer function is used.