Optical lithography extension with double patterning

A more accurate and precise control of overlay performance in lithography process is required as design rule shrinks. Overlay performance is mainly determined by alignment and overlay measurement process, of which alignment and overlay marks play an important role. SADP (Self-aligned double patterning) process becomes widely adopted to realize half pitch of original design for 14nm technology node and beyond. The alignment and overlay marks formed by SADP process differ from traditional ones, which should be well designed to better comply with process condition and reduce the pattern loading effect induced by CMP and ETCH process, and eventually improve overlay performance. In this paper, the alignment behavior of different alignment marks formed via SADP process is investigated. On the other side, the overlay performance of segmented overlay marks is designed and compared with traditional ones to reveal the effect of segmentation on improving the overlay measurement precision and accuracy.

The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer. This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.

Overlay performance has been a critical factor for advanced semiconductor manufacturing for years. Over time these requirements become more stringent as design rules shrink. Overlay mark design and selection are the first two steps of overlay control, and it is known that different overlay mark designs will have different responses to process conditions. An overlay mark optimized for traditional process might not be suitable for SADP (self-aligned double patterning) technology due to changes in lithography and etching process conditions. For instance, the traditional BIB (box-in-box) target defined by the core mask becomes a template structure in SADP flow, the pitch and cycle of the overlay mark is further changed after spacer formation and core film removal hence the mark recognition and robustness have been challenging for the subsequent process layers. The comprehensive study on the methodology of overlay mark design and selection is still not available for SADP process. In this paper, various types of overlay marks were designed to comply with the SADP process to get rid of the weaknesses of traditional targets. TMU (total measurement uncertainty) performance was adopted to determine the optimal overlay marks for meeting production overlay control requirements in SADP process flow. The results have suggested the segmented marks outperform to non-segmented marks on image contrast as well as TMU.

Manufacturing has been incapable of keeping up with Moore's law without significantly increasing process variability and imposing massive geometric restrictions on design. This paper highlights the design impact of variability and geometric constraints - including traditional design rules and pattern-scale constraints - and describes our approach for evaluating and enforcing pattern-scale restrictions on design.

EUV is an ongoing industry challenge to adopt due to its current throughput limitations. The approach to improve throughput has primarily been through a significant focus on source power which has been a continuing challenge for the industry. The subject of this paper is to review and investigate the application of SADP (Self aligned double patterning) as a speed enhancing technique for EUV processing. A process with the potential of running a 16 nm self-aligned final etched pattern in less than 10mJ exposure range is proposed. Many of the current challenges with shot noise and resolution change significantly when SADP is used in conjunction with EUV. In particular, the resolution challenge for a 16nm HP final pattern type image changes to 32nm as an initial pattern requirement for the patterned CD. With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry where the relaxation of both LER and CD together combined, give the resist formulation space a new target when EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final 16nm half pitch target pattern to align with the industry needs. If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added costs associated with the double patterning process. This flow can then be shown to be an enabling approach for many EUV applications.

For the development of the most cost effective lithographic solutions for the 22nm node, the lithographic process and relevant requirements on CDU and overlay need to be identified. In this work, 22nm logic SRAM is selected as use case because FinFET SRAM cells are considered to be a potentia l successor to conventional planar transistors for 22nm node chips. We focus on the back-end layers of FinFET SRAM, including metal and contact. Litho solutions simulated under ideal scanner conditions with the ASML Brion Tachyon TM SMO product are shown. This tool co-optimizes a pixilated freeform source and a continuous transmission gray tone mask based on merit functions of edge placement error. Per scenario, these simulations result in a set of preferred litho solutions with respective source and mask. These solutions have to comply with an imaging metric characterized by MEEF and common PW based on typical fab requirements. In a second step the previously generated solutions are evaluated for CDU analysis using realistic scanner error budget. The purpose is to predict the CDU performance of scanner, process and reticle in order to identify the major contributors for every scenario solution. Keywords: source mask optimization (SMO), single exposure (SE), double exposure (DE), double patterning technology (DPT), Litho-Etch-Litho-Et ch (LELE), CD uniformity (CDU), Fin Field Effect Transistor (FinFET)

Self-aligned double patterning (SADP) is being applied to 7nm technology node and below for back-end metal layers (routing layers) with pitches down to ~40nm. Unlike the traditional litho-etch-litho-etch (LELE) approach, SADP splits pitch using spacers whose 2nd pattern (Color-B) is self-aligned to its 1st pattern (Color-A). As a result, the SADP approach produces less variation than LELE approach by removing the second pattern misalignment on Si. Although SADP provides better overlay controllability than LELE, it still encounters many challenges. One of the challenges is controlling the 2nd patterning linewidth and uniformity. In general, the Color-B critical dimension (CD) has a larger variation than Color-A CD in the SADP process using Mandrel structure. In this paper, we investigate variations to the SADP Color-B CD based on self-aligned litho-etch litho-etch (SALELE) process flow, including the lithographic CD uniformity, hard mask etching, spacer etch and final Si etch. The corresponding contribution to Color-B CD variation is analyzed each step. After the major contributors to Color-B variation are identified, an experiment was designed to reduce Color-B pattern variation during the process. The silicon results show that compared with the old process condition, the new process can reduce Color-B variation significantly. With this new process, Color-B variation is comparable to Color-A variation.

Background: Overlay (OV) is a very important indicator for characterizing the pattern position accuracy between two layers in an integrated circuit in the manufacturing industry. The self-aligned double-patterning (SADP) process, which is limited to the resolution of deep ultraviolet lithography, is being extensively used for the volume manufacturing of integrated circuits. However, compared to the planar process, the SADP process poses new challenges for OV control.Aim: We investigate the bottom grating asymmetry of a microdiffraction-based overlay (μDBO) target in the SADP process and its effect on OV measurement.Approach: The bottom grating of the OV metrology target is analyzed through scanning electron microscopy and transmission electron microscopy. The imbalance of the −1st- and +1st-order diffraction light intensities of the asymmetrical bottom OV target is characterized. Finally, the effects of light polarization and wavelength on the OV accuracy are simulated.Results: Asymmetric behavior of bottom OV grating is identified. OV dependency on the measurement-light polarization is determined. The simulation results indicate that wavelength and polarization affect the OV accuracy simultaneously.Conclusions: We studied the bottom grating asymmetry-induced inaccuracy in DBO measurement and can assist in understanding the mechanism of measurement light-interaction with the OV grating to enhance the DBO accuracy to a new level.

Double patterning lithography (DPL) is the most likely manufacturing process for sub-32nm technology nodes; however, there are several double patterning strategies each of which exhibits different layout decomposition challenges. Self-aligned double patterning (SADP) has attracted much interest due to its robustness against overlay errors, but SADP compliance depends strongly on the characteristics of the individual masks generated during the layout decomposition. This work establishes SADP decomposition requirements and proposes a litho-friendly layout decomposition method. First, we explain the main parameters that limit printability of SADP decomposed layouts. In-silico experiments indicate that layout patterns which are printed by the Trim mask may experience the highest levels of image transfer sensitivity. For that reason, these patterns should be assisted by sidewalls of spacer patterns which are robustly printed. Next, we present an ILP-based decomposition method which avoids decomposition conflicts and sensitive Trim edges simultaneously. Our experiments on several industrial designs reveal that the proposed method decreases the total length of sensitive Trim patterns and consequently reduces the overall edge placement error significantly.

Photolithography has been a driving force behind semiconductor scaling, but the technology has been at a standstill since the development of 193-nm water-based immersion lithography. As a consequence, the double patterning process has become the standard technology for diverse types of semiconductor devices as a means of extending the life of 193-nm exposure technology. We have previously reported on the extendibility and versatility of the double patterning process, from pitch-doubling by self-aligned double patterning (SADP)[1] to pitch-quadrupling by self-aligned quadruple patterning (SAQP)[2]. We also reported on the effectiveness of SADP technology for increasing resolution in hole patterns. While waiting for the development of extreme ultraviolet (EUV) lithography tools to be completed, it will be necessary to search out possibilities for further semiconductor scaling using the double patterning process as the mainstream technique for extending the life of 193-nm immersion lithography.

As the technology nodes scale down to sub-22 nm, double patterning lithography has been considered as a practical solution for layout manufacturing. Compared with litho-etch-litho-etch, self-aligned double patterning (SADP) has better overlay control. To have a better SADP layout decomposability of routing patterns, we consider SADP during detailed routing stage. Two major types of SADP processes are considered: 1) spacer-is-dielectric type and 2) spacer-is-metal type. Different from previous works, the idea of color preassignment is adopted for SADP-aware detailed routing. An elegant graph model is proposed to capture both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules in detailed routing. We apply a negotiated congestion based rip-up and reroute scheme to achieve better routability while maintaining SADP design rules. Compared with other state-of-the-art academic works, our approach does not produce any side overlay error and no SADP design rules violation is reported. Meanwhile, a better solution in terms of total wirelength, routability, and runtime is achieved.

New alignment mark designs in single patterning and self-aligned double patterning

Lithographic scaling has been driven by improvements in wavelength and numerical aperture historically. In the semiconductor industry, the H2O base 192 immersion technique has still been main exposure tool combined with various low-k1 techniques, such like off-axis illumination, phase-shift mask and so on. The focus is now on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh′s definition. Actually, self-aligned spacer double patterning (SADP) has already been employed in high volume manufacturing of NAND flash memory devices. This paper introduces demonstration results focused on the extendibility of double patterning techniques for downward scaling and various device layouts utilizing SADP (Self-aligned Double patterning) mainly.

Among double patterning techniques, Self-aligned double patterning (SADP) has the advantage of good mask overlay control, which has made SADP a popular double patterning method for sub-32nm technology nodes. However, SADP process places several limitations on design flexibility. This work exploits an alternative post routing approach that has the flexibility to resolve lithography violations without the overhead of repeated rule checking. In addition, it allows for successive refinement in the definition of lithographic violations as the process node matures, and implementation of fixes as localized ECO (Engineering Change Order) operations without needing to reroute the complete design.

With extreme UV not ready for HVM for the 20nm and 14nm nodes, double patterning options that extend the use of 193nm immersion lithography beyond the optical resolution limits, such as LELE (Litho-Etch-Litho-Etch) and SADP (Self Aligned Double Patterning), are being used for critical layers for these nodes. LELE requires very stringent overlay capability of the optical exposure tool. The spacer scheme of SADP starts with a conformal film of material around the mandrels and etched along the mandrel sidewalls to form patterns with doubled frequency. SADP, while having the advantage of being a self-aligned process, adds a number of process steps and strict control of the mandrel profile is required. In this paper, we will demonstrate a novel technique - ASDP (Anti-Spacer Double Patterning), which uses only spin-on materials to achieve self-aligned double patterning. After initial resist patterning, an Anti-Spacer Generator (ASG) material is coated on the resist pattern to create the developable spacer region. Another layer of material is then coated and processed to generate the second pattern in between the first resist pattern. We were able to define 37.5nm half pitch pattern features using this technique as well as sub-resolution features for an asymmetric pattern. In this paper we will review the capability of the process in terms of CD control and LWR (line width roughness) and discuss the limitations of the process.