Overlay target design and evaluation for SADP process

A more accurate and precise control of overlay performance in lithography process is required as design rule shrinks. Overlay performance is mainly determined by alignment and overlay measurement process, of which alignment and overlay marks play an important role. SADP (Self-aligned double patterning) process becomes widely adopted to realize half pitch of original design for 14nm technology node and beyond. The alignment and overlay marks formed by SADP process differ from traditional ones, which should be well designed to better comply with process condition and reduce the pattern loading effect induced by CMP and ETCH process, and eventually improve overlay performance. In this paper, the alignment behavior of different alignment marks formed via SADP process is investigated. On the other side, the overlay performance of segmented overlay marks is designed and compared with traditional ones to reveal the effect of segmentation on improving the overlay measurement precision and accuracy.

Self-aligned double patterning (SADP) is being applied to 7nm technology node and below for back-end metal layers (routing layers) with pitches down to ~40nm. Unlike the traditional litho-etch-litho-etch (LELE) approach, SADP splits pitch using spacers whose 2nd pattern (Color-B) is self-aligned to its 1st pattern (Color-A). As a result, the SADP approach produces less variation than LELE approach by removing the second pattern misalignment on Si. Although SADP provides better overlay controllability than LELE, it still encounters many challenges. One of the challenges is controlling the 2nd patterning linewidth and uniformity. In general, the Color-B critical dimension (CD) has a larger variation than Color-A CD in the SADP process using Mandrel structure. In this paper, we investigate variations to the SADP Color-B CD based on self-aligned litho-etch litho-etch (SALELE) process flow, including the lithographic CD uniformity, hard mask etching, spacer etch and final Si etch. The corresponding contribution to Color-B CD variation is analyzed each step. After the major contributors to Color-B variation are identified, an experiment was designed to reduce Color-B pattern variation during the process. The silicon results show that compared with the old process condition, the new process can reduce Color-B variation significantly. With this new process, Color-B variation is comparable to Color-A variation.

The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer. This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.

The integrated circuit (IC) manufacturing factories have measured overlay with conventional "box-in-box" (BiB) or "frame-in-frame" (FiF) structures for many years. Since UMC played as a roll of world class IC foundry service provider, tighter and tighter alignment accuracy specs need to be achieved from generation to generation to meet any kind of customers' requirement, especially according to International Technology Roadmap for Semiconductors (ITRS) 2003 METROLOGY section1. The process noises resulting from dishing, overlay mark damaging by chemical mechanism polishing (CMP), and the variation of film thickness during deposition are factors which can be very problematic in mark alignment. For example, the conventional "box-in-box" overlay marks could be damaged easily by CMP, because the less local pattern density and wide feature width of the box induce either dishing or asymmetric damages for the measurement targets, which will make the overlay measurement varied and difficult. After Advanced Imaging Metrology (AIM) overlay targets was introduced by KLA-Tencor, studies in the past shown AIM was more robust in overlay metrology than conventional FiF or BiB targets. In this study, the applications of AIM overlay marks under different process conditions will be discussed and compared with the conventional overlay targets. To evaluate the overlay mark performance against process variation on 65nm technology node in 300-mm wafer, three critical layers were chosen in this study. These three layers were Poly, Contact, and Cu-Metal. The overlay targets used for performance comparison were BiB and Non-Segmented AIM (NS AIM) marks. We compared the overlay mark performance on two main areas. The first one was total measurement uncertainty (TMU)3 related items that include Tool Induced Shift (TIS) variability, precision, and matching. The other area is the target robustness against process variations. Based on the present study AIM mark demonstrated an equal or better performance in the TMU related items under our process conditions. However, when non-optimized tungsten CMP was introduced in the tungsten contact process, due to the dense grating line structure design, we found that AIM mark was much more robust than BiB overlay target.

Background: An overlay target design is essential before performing overlay metrology and has a great impact on overlay performance. In addition, accurate overlay metrology is required to achieve high product yields in semiconductor manufacturing. When asymmetry of the overlay target occurs, it is necessary to increase the area of the pattern existing in the target and stabilize the optical aberration for stable measurement. For this reason, we propose an image-based overlay target design that can secure a larger area compared with the existing overlay target and stabilize the optical aberration by overlapping and exposing the upper and lower patterns of the overlay target.Aim: The effective area of the existing mark design is improved by proposing an overlay target and a measurement method used in image-based overlay measurement.Approach: The proposed overlay target design is configured by arranging different marks orthogonally to the upper and lower layers, and different two-dimensional information can be inserted in the same area. When necessary, single-dimensional information desired by the user can be obtained through a technique called projection, and it has the advantage of using a larger effective area than the existing overlay target.Results: Overlay can be measured using projected signal components, and the possibility and performance of the proposed target can be confirmed through simulation and test wafer. In addition, it was possible to bring about a 15% improvement in total measurement uncertainty performance compared with the existing advanced imaging metrology (AIM) target by taking a wider effective area.Conclusions: An overlay target design is proposed to solve the technical problems of the existing overlay target design. The proposed overlay target has a method that is capable of minimizing the size of the overlay target while maximally maintaining the signal density, a way of reducing the influence of aberration, and various other advantages.In addition, the proposed method provides a design rule that breaks the “lower pattern and upper pattern must not overlap” framework.

Background: Overlay (OV) is a very important indicator for characterizing the pattern position accuracy between two layers in an integrated circuit in the manufacturing industry. The self-aligned double-patterning (SADP) process, which is limited to the resolution of deep ultraviolet lithography, is being extensively used for the volume manufacturing of integrated circuits. However, compared to the planar process, the SADP process poses new challenges for OV control.Aim: We investigate the bottom grating asymmetry of a microdiffraction-based overlay (μDBO) target in the SADP process and its effect on OV measurement.Approach: The bottom grating of the OV metrology target is analyzed through scanning electron microscopy and transmission electron microscopy. The imbalance of the −1st- and +1st-order diffraction light intensities of the asymmetrical bottom OV target is characterized. Finally, the effects of light polarization and wavelength on the OV accuracy are simulated.Results: Asymmetric behavior of bottom OV grating is identified. OV dependency on the measurement-light polarization is determined. The simulation results indicate that wavelength and polarization affect the OV accuracy simultaneously.Conclusions: We studied the bottom grating asymmetry-induced inaccuracy in DBO measurement and can assist in understanding the mechanism of measurement light-interaction with the OV grating to enhance the DBO accuracy to a new level.

As the technology nodes scale down to sub-22 nm, double patterning lithography has been considered as a practical solution for layout manufacturing. Compared with litho-etch-litho-etch, self-aligned double patterning (SADP) has better overlay control. To have a better SADP layout decomposability of routing patterns, we consider SADP during detailed routing stage. Two major types of SADP processes are considered: 1) spacer-is-dielectric type and 2) spacer-is-metal type. Different from previous works, the idea of color preassignment is adopted for SADP-aware detailed routing. An elegant graph model is proposed to capture both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules in detailed routing. We apply a negotiated congestion based rip-up and reroute scheme to achieve better routability while maintaining SADP design rules. Compared with other state-of-the-art academic works, our approach does not produce any side overlay error and no SADP design rules violation is reported. Meanwhile, a better solution in terms of total wirelength, routability, and runtime is achieved.

The present study sought to determine how the overlay design and performance of asphalt concrete (AC) were affected by existing pavement condition and overlay material properties. To that end, this study was performed in different scenarios of traffic and structure with the latest AASHTO design software AASHTOWare (version 2.3). The modulus and rut depth of existing layers, the interface condition between AC overlay and existing pavement, and the AC overlay properties of Poisson’s ratio and performance grade were addressed in the current study. Besides the overlay thickness design, the investigation also focused on pavement performance to determine how separate distresses were impacted by existing pavement condition and the properties of the overlay material. The investigation produced three major outcomes, as follows: the current AC layer thickness and design traffic determined the extent to which the existing AC layer condition affected the overlay design thickness; the overlay performance and design were not significantly affected by the existing base and subgrade condition; and fatigue cracking was more strongly influenced by the existing AC layer modulus and interface bonding condition compared with the rutting potential.

New alignment mark designs in single patterning and self-aligned double patterning

Design shrinking beyond the resolution limits of 193 nm optical lithography requires the introduction of double patterning technology (DPT) for the semiconductor industry. Two consecutive lithography and etching process (LELE; Litho-Etch-Litho-Etch) and self aligned double patterning (SADP) process are major two options of DPT.In LELE process, layout patterns are decomposed into two groups and each group is placed on a photo mask. The original layout is reconstructed on a wafer through two lithography with two those photo masks. The two lithography processes are independent because of the intermediate process in between, such as etching and resist freeze. Lithography conditions for each mask are optimized on source mask optimization (SMO) technique to enlarge lithography margin. Conventional SMO technique can be applied to the decomposed patterns since two lithography processes have no interaction as discussed above.In SADP process, a layout is also decomposed into two groups as same as the methodology for LELE process. Either decomposed group is transferred on a wafer, which is named as mandrel. Sidewalls are deposited on the mandrel patterns and the following processes such as etching and mandrel removal reconstruct the original layout.Design rules for DPT consist of two parts. One is for an original layout which is drawn by designers. The other is for each decomposed layout printed by a lithography process. Both design rules have interactions because the original layout which follows the former design rules is decomposed into two groups which follow the latter design rules.In this paper, we will discuss the relation between the two rules above. Furthermore, we will discuss the situation on triple or quadruple patterning.

The requirement of overlay performance, which is determined by alignment process during exposure and overlay measurement process, is getting tighter as technology node shrinks in integrated circuit. Mark design has drawn a lot of attention since appropriately designed marks can guarantee process compatibility and sufficient device performance tracking property. Cut layers are widely used in FinFet to define active area formed by SADP (Self-aligned double patterning) or SAQP (Self-aligned quadruple patterning), of which the mark design is especially challenging for diffusion break layer since it is a cut layer that landing on three dimensional fin structure and will be aligned to. In this paper, mark design of diffusion break layer is investigated, including alignment marks and overlay marks with various substrates and segmentations. It’s recommended that the whole process from mark definition by lithography to final formation of mark after etch should be well taken into consideration during mark design, along with substrate and segmentation to avoid defect and achieve qualified signal as well.

Among double patterning techniques, Self-aligned double patterning (SADP) has the advantage of good mask overlay control, which has made SADP a popular double patterning method for sub-32nm technology nodes. However, SADP process places several limitations on design flexibility. This work exploits an alternative post routing approach that has the flexibility to resolve lithography violations without the overhead of repeated rule checking. In addition, it allows for successive refinement in the definition of lithographic violations as the process node matures, and implementation of fixes as localized ECO (Engineering Change Order) operations without needing to reroute the complete design.

In a previous publication, we introduced Blossom, a multi-layer overlay mark (Ausschnitt, et al. 2006, [1]). Through further testing carried out since that publication, Blossom has been shown to meet the requirements on current design rules (Ausschnitt, et al. 2007, [2]), while giving some unique benefits. However, as future design rules shrink, efforts must be made now to ensure the extensibility of the Blossom technology. Previous work has shown that the precision component of Total Measurement Uncertainty (TMU) can be reduced by using extra redundancy in the target design, to achieve performance beyond that of a conventional box-in-box measurement. However, improvements that single contributor to TMU would not be sufficient for future design rules; therefore we have also to consider the Tool Induced Shift (TIS) variability and tool to tool matching contributions to TMU. In this paper, we introduce a calibration artifact, based on the Blossom technology. The calibration artifact is both compact, and produced by standard lithography process, so it can be placed in a production scribe line if required, reducing the need for special sets of calibration wafers compared to other possible calibration methodologies. Calibration is currently with respect to the exposure tool / process / mask, which is arguably more pertinent to good yield, and less expensive, than calibration to an external standard; externally calibrated artifacts would be straightforward to manufacture if needed. By using this artifact, we can map out remaining optical distortions within an overlay tool, to a precision significantly better than the operational tool precision, in a way that directly relates to overlay performance. The effect of process-induced mark uncertainties on calibration can be reduced by performing measurements on a large number of targets; by taking multiple measurements of each target we can also use the artifact to evaluate the current levels of process induced mark uncertainty. The former result leads to an improvement method for TIS and matching capability. We describe the artifact and its usage, and present results from a group of operational overlay tools. We show how the use of this information also provides further insight into the layout optimizations discussed previously (Binns et al. 2006 [3]). It provides the current limits of measurement precision and mark fidelity with respect to target redundancy, enabling us to use a predictive cost-benefit term in the optimization. Finally, examining the bulk behaviour of a fleet of overlay tools, allows us to examine how future mark layouts can also contribute to minimizing TMU rather than just precision.

Self-aligned double patterning (SADP) is one of the most promising techniques for sub-20 nm technology. Spacer-is-dielectric SADP using a cut process is getting popular because of its higher design flexibility; for example, it can decompose odd cycles without the need of inserting any stitch. This paper presents the first work that applies the cut process for decomposing odd cycles during routing. For SADP, further, overlay control is a critical issue for yield improvement; while published routers can handle only partial overlay scenarios, this paper identifies all the scenarios that induce overlays and proposes a novel constraint graph to model all overlays. With the developed techniques, our router can achieve high-quality routing results with significantly fewer overlays (and thus better yields). Compared with three state-of-the-art studies, our algorithm can achieve the best quality and efficiency, with zero cut conflicts, smallest overlay length, highest routability, and fastest running time.

This paper reports a systematic approach for characterizing and optimizing overlay target design to minimize the overlay target noise for shallow trench isolation (STI) process. Sixteen overlay targets were designed and evaluated to determine which target result in the most accurate and reproducible overlay measurements for STI process. The experiment conducted consists of two phase: the first phase is target screening for evaluating sixteen different target designs on STI laser. Each overlay target design is characterized by quantifying the mean TIS, TIS variability, target step height variance, dynamic precision , overlay measurement distribution, kernels signal and modeled residuals. Also, four one-layer inner and outer calibration targets were placed next to the sixteen targets to evaluate the CMP distortion effect on the overlay targets. In the second, phase, short and long-term gauge studies were performed. Stepper offset and correction were tested to verify the accuracy of overlay response. A design of experiment was completed to check robustness of overlay target to process variation in nitride thickness and CMP polishing time with and without the stepper alignment mark clear out process. Overlay measurement accuracy is correlated with SEM cross section to complete the evaluation.