Bottom grating asymmetry-induced inaccuracy in diffraction-based overlay measurement

The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer. This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.

A more accurate and precise control of overlay performance in lithography process is required as design rule shrinks. Overlay performance is mainly determined by alignment and overlay measurement process, of which alignment and overlay marks play an important role. SADP (Self-aligned double patterning) process becomes widely adopted to realize half pitch of original design for 14nm technology node and beyond. The alignment and overlay marks formed by SADP process differ from traditional ones, which should be well designed to better comply with process condition and reduce the pattern loading effect induced by CMP and ETCH process, and eventually improve overlay performance. In this paper, the alignment behavior of different alignment marks formed via SADP process is investigated. On the other side, the overlay performance of segmented overlay marks is designed and compared with traditional ones to reveal the effect of segmentation on improving the overlay measurement precision and accuracy.

In 32nm/22nm advanced technology node, double patterning lithography is considered for semiconductor manufacturing. It necessitates tightened requirement of overlay measurement, i.e. to measure the position of a pattern with respect to that of a pattern in the underlying layer. The measurement target design plays a fundamental role in overlay precision and accuracy. Typical alignment target, such as bar-in-bar or box-in-box (BIB), has precision, accuracy, and size restrictions. This prompts us to look into better alignment targets. Recently, scatterometry-based metrology and profile model capability have been extended to measure multi-level grating structures. In addition, scatterometry has been shown to be the best choice for integrated metrology to perform wafer-to-wafer control. Therefore, it makes sense to consider using scatterometry for overlay measurement. In this research, the modeling analysis is performed on the spectra taken directly from a real pattern area with grating-ongrating structure. The critical dimension (CD) at the grating on top and the lateral shift between the top and the bottom gratings can be detected simultaneously. The lateral shift between the layers can be verified with the traditional overlay box. Unlike the traditional BIB target that has micrometer CD size, the CD size of the scatterometry overlay (S_OVL) target is much closer to that on the real device. So, it can much better reflect the overlay (OVL) shift on real devices. We also studied the non-model-based S_OVL measurement using a 673-nm semiconductor laser with a 10μm x 20μm target size, wafer-to-wafer control of CD and lateral shifts on some critical layers with grating-on-grating structure, as well as the CD and OVL variations within layer and from layer to layer for double patterning.

Overlay performance has been a critical factor for advanced semiconductor manufacturing for years. Over time these requirements become more stringent as design rules shrink. Overlay mark design and selection are the first two steps of overlay control, and it is known that different overlay mark designs will have different responses to process conditions. An overlay mark optimized for traditional process might not be suitable for SADP (self-aligned double patterning) technology due to changes in lithography and etching process conditions. For instance, the traditional BIB (box-in-box) target defined by the core mask becomes a template structure in SADP flow, the pitch and cycle of the overlay mark is further changed after spacer formation and core film removal hence the mark recognition and robustness have been challenging for the subsequent process layers. The comprehensive study on the methodology of overlay mark design and selection is still not available for SADP process. In this paper, various types of overlay marks were designed to comply with the SADP process to get rid of the weaknesses of traditional targets. TMU (total measurement uncertainty) performance was adopted to determine the optimal overlay marks for meeting production overlay control requirements in SADP process flow. The results have suggested the segmented marks outperform to non-segmented marks on image contrast as well as TMU.

Self-aligned double patterning (SADP) is being applied to 7nm technology node and below for back-end metal layers (routing layers) with pitches down to ~40nm. Unlike the traditional litho-etch-litho-etch (LELE) approach, SADP splits pitch using spacers whose 2nd pattern (Color-B) is self-aligned to its 1st pattern (Color-A). As a result, the SADP approach produces less variation than LELE approach by removing the second pattern misalignment on Si. Although SADP provides better overlay controllability than LELE, it still encounters many challenges. One of the challenges is controlling the 2nd patterning linewidth and uniformity. In general, the Color-B critical dimension (CD) has a larger variation than Color-A CD in the SADP process using Mandrel structure. In this paper, we investigate variations to the SADP Color-B CD based on self-aligned litho-etch litho-etch (SALELE) process flow, including the lithographic CD uniformity, hard mask etching, spacer etch and final Si etch. The corresponding contribution to Color-B CD variation is analyzed each step. After the major contributors to Color-B variation are identified, an experiment was designed to reduce Color-B pattern variation during the process. The silicon results show that compared with the old process condition, the new process can reduce Color-B variation significantly. With this new process, Color-B variation is comparable to Color-A variation.

Design shrinking beyond the resolution limits of 193 nm optical lithography requires the introduction of double patterning technology (DPT) for the semiconductor industry. Two consecutive lithography and etching process (LELE; Litho-Etch-Litho-Etch) and self aligned double patterning (SADP) process are major two options of DPT.In LELE process, layout patterns are decomposed into two groups and each group is placed on a photo mask. The original layout is reconstructed on a wafer through two lithography with two those photo masks. The two lithography processes are independent because of the intermediate process in between, such as etching and resist freeze. Lithography conditions for each mask are optimized on source mask optimization (SMO) technique to enlarge lithography margin. Conventional SMO technique can be applied to the decomposed patterns since two lithography processes have no interaction as discussed above.In SADP process, a layout is also decomposed into two groups as same as the methodology for LELE process. Either decomposed group is transferred on a wafer, which is named as mandrel. Sidewalls are deposited on the mandrel patterns and the following processes such as etching and mandrel removal reconstruct the original layout.Design rules for DPT consist of two parts. One is for an original layout which is drawn by designers. The other is for each decomposed layout printed by a lithography process. Both design rules have interactions because the original layout which follows the former design rules is decomposed into two groups which follow the latter design rules.In this paper, we will discuss the relation between the two rules above. Furthermore, we will discuss the situation on triple or quadruple patterning.

New alignment mark designs in single patterning and self-aligned double patterning

BackgroundThe self-aligned double-patterning (SADP) process is being used extensively to overcome the lithographic resolution limit in the manufacture of integrated circuits. One use case is fin definition in a fin field-effect transistor. Fin cut layers are applied to modify the fins to the requirements of the device designs.AimThe traditional secondary electron (SE) imaging exhibits a disadvantage in the process controlling the fin cut layers, and fin damage defects were observed. This work aims to improve the monitoring and controlling capabilities for the process quality of fin cut layers.ApproachA specially designed fin cut process flow and a backscattered electron (BSE) imaging technique are applied to check the process quality. The patterns formed through the fin cut etch and the fin structures are identified and measured simultaneously in one BSE image.ResultsBy measuring the edge-to-edge distance, pitch walking (PW) of fins, and overlay (OV), the root cause of the fin damage is revealed. The linear fitting model and third-order fitting model are applied to reduce the edge placement error (EPE). The edge distance protecting the “at risk” fin is enlarged from 5.6 to 11.6 nm. The range of the distance is reduced from 11.6 to 8.1 nm, and the improvement in standard deviation is about 33%.ConclusionsThis work shows the capability of the BSE imaging technique in the characterization of fin cut layers and the potential in process window improvement restricted to fin damage defects.

Overlay (OVL) is one significant performance indicator for the lithography process control in semiconductor manufacturing. The accuracy of the OVL metrology is extremely critical for guarantee the lithography quality. Currently, diffraction-based overlay (DBO) is one of the mainstream OVL metrology techniques. Unfortunately, the accuracy of the DBO metrology is largely affected by the defect features of the OVL target. Therefore, there is a strong need to investigate the impacts of these target defects on the DBO metrology performance. However, efficiently investigating the statistical and interactive impacts of various DBO target defects remains challenging. This study aims to address this issue through proposing an intelligent sensitivity analysis approach. A cumulative distribution based global sensitivity analysis (GSA) method is utilized to assess the nonlinear influences of multiple defects in the OVL target on the DBO inaccuracy. The scenarios with both known and unknown distributions of the OVL target defects are considered. For the former, a neural network driven forward model is constructed for fast calculating the optical diffraction responses to accelerate the GSA process. For the latter, another neural network based inverse model are built for efficiently estimating the distribution of the target defects. Finally, a series of simulation experiments are conduct for typical DBO targets with multiple common defect features. The results demonstrate the effectiveness and robustness of the proposed approach as well as give valuable insights into the DBO defect analysis. Our study provides a strong tool to assist the practitioners in achieving intelligent and efficient DBO analysis and thus in enhancing OVL metrology performance.

As the design rule of semiconductor devices shrinks to below 100nm dimensions, the degree of pattern alignment from different process levels has become a crucial factor affecting both process control and induced defect on unit process. Isolated and dense patterns were formed at process layers from front-end through to back-end on wafers using sub 100nm device process utilizing ArF lithography under various lithography conditions. As pattern size is reduced, overlay discrepancies become larger. The OL (overlay) error is very important because the pattern misalignment induces critical defects for the device. For many years, overlay metrology for process control has been measured by 4-corner box-in-box methods in chip. OL errors and CD (Critical Dimension) values have been measured on different tool. CD values have been measured on SEMs (Scanning Electron Microscope) and OL errors have been measured on optical tools. The accuracy of OL error metrology is limited by the resolution of tool, which is on the order of 1μm. In this paper we calculated the degree of overlay errors (current level to prior level errors) through a process patterns images obtained from a CD-SEM.

As the technology nodes scale down to sub-22 nm, double patterning lithography has been considered as a practical solution for layout manufacturing. Compared with litho-etch-litho-etch, self-aligned double patterning (SADP) has better overlay control. To have a better SADP layout decomposability of routing patterns, we consider SADP during detailed routing stage. Two major types of SADP processes are considered: 1) spacer-is-dielectric type and 2) spacer-is-metal type. Different from previous works, the idea of color preassignment is adopted for SADP-aware detailed routing. An elegant graph model is proposed to capture both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules in detailed routing. We apply a negotiated congestion based rip-up and reroute scheme to achieve better routability while maintaining SADP design rules. Compared with other state-of-the-art academic works, our approach does not produce any side overlay error and no SADP design rules violation is reported. Meanwhile, a better solution in terms of total wirelength, routability, and runtime is achieved.

EUV is an ongoing industry challenge to adopt due to its current throughput limitations. The approach to improve throughput has primarily been through a significant focus on source power which has been a continuing challenge for the industry. The subject of this paper is to review and investigate the application of SADP (Self aligned double patterning) as a speed enhancing technique for EUV processing. A process with the potential of running a 16 nm self-aligned final etched pattern in less than 10mJ exposure range is proposed. Many of the current challenges with shot noise and resolution change significantly when SADP is used in conjunction with EUV. In particular, the resolution challenge for a 16nm HP final pattern type image changes to 32nm as an initial pattern requirement for the patterned CD. With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry where the relaxation of both LER and CD together combined, give the resist formulation space a new target when EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final 16nm half pitch target pattern to align with the industry needs. If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added costs associated with the double patterning process. This flow can then be shown to be an enabling approach for many EUV applications.

Photolithography has been a driving force behind semiconductor scaling, but the technology has been at a standstill since the development of 193-nm water-based immersion lithography. As a consequence, the double patterning process has become the standard technology for diverse types of semiconductor devices as a means of extending the life of 193-nm exposure technology. We have previously reported on the extendibility and versatility of the double patterning process, from pitch-doubling by self-aligned double patterning (SADP)[1] to pitch-quadrupling by self-aligned quadruple patterning (SAQP)[2]. We also reported on the effectiveness of SADP technology for increasing resolution in hole patterns. While waiting for the development of extreme ultraviolet (EUV) lithography tools to be completed, it will be necessary to search out possibilities for further semiconductor scaling using the double patterning process as the mainstream technique for extending the life of 193-nm immersion lithography.

Among double patterning techniques, Self-aligned double patterning (SADP) has the advantage of good mask overlay control, which has made SADP a popular double patterning method for sub-32nm technology nodes. However, SADP process places several limitations on design flexibility. This work exploits an alternative post routing approach that has the flexibility to resolve lithography violations without the overhead of repeated rule checking. In addition, it allows for successive refinement in the definition of lithographic violations as the process node matures, and implementation of fixes as localized ECO (Engineering Change Order) operations without needing to reroute the complete design.

Amongst the possible double patterning strategies for sub 32nm processes, self-aligned double patterning (SADP) has moved from Flash-only processes to more general purpose devices. The reason is that while litho-etch- litho-etc (LELE) process was originally preferred due to its simplicity and relative low cost, its sensitivity to overlay error has prompted the search for other methods. Although the basic SADP process is fairly robust against the overlay error, the robustness of 2D SADP method strongly depends on layout and decomposition styles and decomposability compliance. In this paper, we first discuss different printability challenges for SADP method. Afterward, we propose a SADP-aware detailed routing method, by applying a correct-by-construction approach, to provide SADP-friendly layouts. This method performs detailed routing and layout decomposition concurrently to prevent litho-limited layout configurations. Experimental results show that, compared with a SADP-blind detailed router, the proposed method achieves considerable robustness against lithography imperfection in expense of tolerable wire length overhead.