High speed EUV using post processing and self-aligned double patterning as a speed enhancement technique

Design shrinking beyond the resolution limits of 193 nm optical lithography requires the introduction of double patterning technology (DPT) for the semiconductor industry. Two consecutive lithography and etching process (LELE; Litho-Etch-Litho-Etch) and self aligned double patterning (SADP) process are major two options of DPT.In LELE process, layout patterns are decomposed into two groups and each group is placed on a photo mask. The original layout is reconstructed on a wafer through two lithography with two those photo masks. The two lithography processes are independent because of the intermediate process in between, such as etching and resist freeze. Lithography conditions for each mask are optimized on source mask optimization (SMO) technique to enlarge lithography margin. Conventional SMO technique can be applied to the decomposed patterns since two lithography processes have no interaction as discussed above.In SADP process, a layout is also decomposed into two groups as same as the methodology for LELE process. Either decomposed group is transferred on a wafer, which is named as mandrel. Sidewalls are deposited on the mandrel patterns and the following processes such as etching and mandrel removal reconstruct the original layout.Design rules for DPT consist of two parts. One is for an original layout which is drawn by designers. The other is for each decomposed layout printed by a lithography process. Both design rules have interactions because the original layout which follows the former design rules is decomposed into two groups which follow the latter design rules.In this paper, we will discuss the relation between the two rules above. Furthermore, we will discuss the situation on triple or quadruple patterning.

Manufacturing has been incapable of keeping up with Moore's law without significantly increasing process variability and imposing massive geometric restrictions on design. This paper highlights the design impact of variability and geometric constraints - including traditional design rules and pattern-scale constraints - and describes our approach for evaluating and enforcing pattern-scale restrictions on design.

Photolithography has been a driving force behind semiconductor scaling, but the technology has been at a standstill since the development of 193-nm water-based immersion lithography. As a consequence, the double patterning process has become the standard technology for diverse types of semiconductor devices as a means of extending the life of 193-nm exposure technology. We have previously reported on the extendibility and versatility of the double patterning process, from pitch-doubling by self-aligned double patterning (SADP)[1] to pitch-quadrupling by self-aligned quadruple patterning (SAQP)[2]. We also reported on the effectiveness of SADP technology for increasing resolution in hole patterns. While waiting for the development of extreme ultraviolet (EUV) lithography tools to be completed, it will be necessary to search out possibilities for further semiconductor scaling using the double patterning process as the mainstream technique for extending the life of 193-nm immersion lithography.

Lithographic scaling has been driven by improvements in wavelength and numerical aperture historically. In the semiconductor industry, the H2O base 192 immersion technique has still been main exposure tool combined with various low-k1 techniques, such like off-axis illumination, phase-shift mask and so on. The focus is now on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh′s definition. Actually, self-aligned spacer double patterning (SADP) has already been employed in high volume manufacturing of NAND flash memory devices. This paper introduces demonstration results focused on the extendibility of double patterning techniques for downward scaling and various device layouts utilizing SADP (Self-aligned Double patterning) mainly.

With extreme UV not ready for HVM for the 20nm and 14nm nodes, double patterning options that extend the use of 193nm immersion lithography beyond the optical resolution limits, such as LELE (Litho-Etch-Litho-Etch) and SADP (Self Aligned Double Patterning), are being used for critical layers for these nodes. LELE requires very stringent overlay capability of the optical exposure tool. The spacer scheme of SADP starts with a conformal film of material around the mandrels and etched along the mandrel sidewalls to form patterns with doubled frequency. SADP, while having the advantage of being a self-aligned process, adds a number of process steps and strict control of the mandrel profile is required. In this paper, we will demonstrate a novel technique - ASDP (Anti-Spacer Double Patterning), which uses only spin-on materials to achieve self-aligned double patterning. After initial resist patterning, an Anti-Spacer Generator (ASG) material is coated on the resist pattern to create the developable spacer region. Another layer of material is then coated and processed to generate the second pattern in between the first resist pattern. We were able to define 37.5nm half pitch pattern features using this technique as well as sub-resolution features for an asymmetric pattern. In this paper we will review the capability of the process in terms of CD control and LWR (line width roughness) and discuss the limitations of the process.

Double patterning lithography (DPL) is the most likely manufacturing process for sub-32nm technology nodes; however, there are several double patterning strategies each of which exhibits different layout decomposition challenges. Self-aligned double patterning (SADP) has attracted much interest due to its robustness against overlay errors, but SADP compliance depends strongly on the characteristics of the individual masks generated during the layout decomposition. This work establishes SADP decomposition requirements and proposes a litho-friendly layout decomposition method. First, we explain the main parameters that limit printability of SADP decomposed layouts. In-silico experiments indicate that layout patterns which are printed by the Trim mask may experience the highest levels of image transfer sensitivity. For that reason, these patterns should be assisted by sidewalls of spacer patterns which are robustly printed. Next, we present an ILP-based decomposition method which avoids decomposition conflicts and sensitive Trim edges simultaneously. Our experiments on several industrial designs reveal that the proposed method decreases the total length of sensitive Trim patterns and consequently reduces the overall edge placement error significantly.

As the technology nodes scale down to sub-22 nm, double patterning lithography has been considered as a practical solution for layout manufacturing. Compared with litho-etch-litho-etch, self-aligned double patterning (SADP) has better overlay control. To have a better SADP layout decomposability of routing patterns, we consider SADP during detailed routing stage. Two major types of SADP processes are considered: 1) spacer-is-dielectric type and 2) spacer-is-metal type. Different from previous works, the idea of color preassignment is adopted for SADP-aware detailed routing. An elegant graph model is proposed to capture both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules in detailed routing. We apply a negotiated congestion based rip-up and reroute scheme to achieve better routability while maintaining SADP design rules. Compared with other state-of-the-art academic works, our approach does not produce any side overlay error and no SADP design rules violation is reported. Meanwhile, a better solution in terms of total wirelength, routability, and runtime is achieved.

This paper presents a unique gate structure for reducing shorts between word lines on charge-trapping flash cell memory. In the early stage of developing sub-45 nm half-pitch word line by a self-aligned double patterning (SADP) technology, the cell array suffered from abnormal intrinsic word line-to-word line shorts, ca. 96.3% of the bridge rate on the 72 Mb cell memory, due to the formation of polysilicon residues called stringers. The increase of polysilicon over-etching to eliminate stringers involves a trade-off between the removal efficiency of stringers and the feature size maintenance. Hence, a novel bottle-shaped gate profile was tailor-made and studied. As a result, the bridge rates are dramatically suppressed to 0%∼10% on the low-density flash cells and ca. 22% in average on the high-density 512 Mb flash cell memory. The novel bottle-shaped gate structure is successfully implemented in advanced charge-trapping flash memory development.

Among double patterning techniques, Self-aligned double patterning (SADP) has the advantage of good mask overlay control, which has made SADP a popular double patterning method for sub-32nm technology nodes. However, SADP process places several limitations on design flexibility. This work exploits an alternative post routing approach that has the flexibility to resolve lithography violations without the overhead of repeated rule checking. In addition, it allows for successive refinement in the definition of lithographic violations as the process node matures, and implementation of fixes as localized ECO (Engineering Change Order) operations without needing to reroute the complete design.

Self-aligned double patterning (SADP) is being applied to 7nm technology node and below for back-end metal layers (routing layers) with pitches down to ~40nm. Unlike the traditional litho-etch-litho-etch (LELE) approach, SADP splits pitch using spacers whose 2nd pattern (Color-B) is self-aligned to its 1st pattern (Color-A). As a result, the SADP approach produces less variation than LELE approach by removing the second pattern misalignment on Si. Although SADP provides better overlay controllability than LELE, it still encounters many challenges. One of the challenges is controlling the 2nd patterning linewidth and uniformity. In general, the Color-B critical dimension (CD) has a larger variation than Color-A CD in the SADP process using Mandrel structure. In this paper, we investigate variations to the SADP Color-B CD based on self-aligned litho-etch litho-etch (SALELE) process flow, including the lithographic CD uniformity, hard mask etching, spacer etch and final Si etch. The corresponding contribution to Color-B CD variation is analyzed each step. After the major contributors to Color-B variation are identified, an experiment was designed to reduce Color-B pattern variation during the process. The silicon results show that compared with the old process condition, the new process can reduce Color-B variation significantly. With this new process, Color-B variation is comparable to Color-A variation.

Self-Aligned-Double-Patterning (SADP) is a potential technology for metal layers in N10 and beyond nodes. SADP manufacturing process comes with lots of challenges. Several approaches were introduced to manufacture SADP. The most major SADP manufacturing approach is the Spacer-Is-Dielectric (SID). One of the main advantages of SADP over Litho-Etch-Litho-Etch (LELE) Double Patterning (DP) is better Mask Overlay Control. In addition, SADP results in better process tolerance and lower Line-Width Roughness. In this paper, we propose a model-based manufacturing flow for SID-SADP approach. The flow includes: (1) SADP Patterns Decomposition, (2) Etch Retargeting, (3) Sub Resolution Assist Features (SRAF) Insertion, (4) Optical Proximity Correction (OPC) process, and finally (5) Verification. The motivation beyond developing this flow is to find the least number of needed masks to achieve satisfactory imaging quality, and to characterize possible challenges in each step of the flow. Consequently, we highlight the challenges and the proposed techniques we examined to meet this objective.

The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer. This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.

In order to continue scaling down the feature sizes of the devices until extreme ultraviolet lithography (EUVL) reaches to production capability, the alternative methods such as double patterning technology (DPT) and spacer patterning technology (SPT) are applied for half pitch (hp) 2x~3x nm line / space imaging. In the storage node of DRAM, both stable hole patterning and high dielectric constant (ε) material development are key factors to secure the capacitance. In terms of hole patterning, we anticipate that hp 4x nm hole will be possible with combination of vertical and horizontal lines. However, the patterning process for hp 3x nm hole has to find a solution in trade-off relationship between process stability, complexity and cost of ownership (CoO) until EUVL is accomplished. In this paper, we will demonstrate 3x nm hole patterning process using double patterning technology combined with negative tone development (NTD). Contrary to general method (positive tone development with dark field mask) for hole patterning, intention to use NTD with bright field mask will first be discussed. Evaluation and analysis of the simulated and experimental results will be discussed for block CD uniformity improvement. In addition to patterning, overlay performance will be tested through NXT 1950i to confirm DPT process feasibility. Finally, process integrations including etch process will be demonstrated.

Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the complexity of parasitic capacitance extractions. In this study, we mainly analyzed the effect of double patterning overlay on the intra-layer capacitance, inter-layer capacitance and process corner.

We consider a memory device that is printed by double patterning (litho-etch-litho-etch) technology wherein positive images of ¹/₄-pitch lines are printed in each patterning step. We analyze the errors that affect the width of the spaces. We propose a graphical method of visualizing the many-dimensional process-window for double patterning. Controlling the space-width to ±10% of half-pitch is not possible under the worst combination of errors. Statistical analysis shows that overlay and etch bias are the most significant contributors to the variability of spaces. 3&sgr;[space-width] = 17% and 11% of nominal space can be achieved for 3&sgr;[Overlay] = 6 nm and 3 nm, respectively, for a 40-nm half pitch array printed using NA=0.93.