Anti-spacer double patterning

Lithographic scaling has been driven by improvements in wavelength and numerical aperture historically. In the semiconductor industry, the H2O base 192 immersion technique has still been main exposure tool combined with various low-k1 techniques, such like off-axis illumination, phase-shift mask and so on. The focus is now on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh′s definition. Actually, self-aligned spacer double patterning (SADP) has already been employed in high volume manufacturing of NAND flash memory devices. This paper introduces demonstration results focused on the extendibility of double patterning techniques for downward scaling and various device layouts utilizing SADP (Self-aligned Double patterning) mainly.

As EUV direct patterning begins to hit its resolution limit, the need for EUV self-aligned double patterning (SADP) has arisen in order to reach sub-30 nm pitch. Currently, EUV resists suffer from several shortcomings, both in terms of roughness and resist budget. These constraints means using it directly as a mandrel material, as previously done for immersion lithography SADP is nearly impossible. Consequently, standard EUV SADP flows involve the transfer of the resist through a lithography stack and into a hard mandrel material, such as silicon nitride or amorphous silicon.¹ Achieving line edge roughness (LER) and line width roughness (LWR) targets for an EUV SADP hard mandrel is significantly more challenging than for EUV direct print since the etch process needs to target a post etch CD of about half that of the lithographic CD. This aggressive shrink requirement usually involves degradation in roughness driven by high aspect ratios. To circumvent these issues, we have developed a new bottom up organic mandrel growth process, whereby the EUV resist can be grown to a height compatible with a resist mandrel SADP flow, while the roughness is improved and the critical dimension is controlled. This bottom up mandrel growth process is performed in an etch chamber and can therefore be easily coupled with other process steps. The mandrel height and critical dimensions can be easily tuned from the incoming lithography by changing the deposition and trim step times of the process. We have shown that this bottom-up grown mandrel can withstand typical ALD spacer process deposition. After spacer open, the organic material can be easily removed through an in-situ ash process before opening the underlayer. This integration will allow for the removal of the organic planarizing layer in the lithography stack, reducing the stack complexity, while also eliminating one of the major contributors to wiggling in the typical hard mandrel patterning scheme. In this paper, the performance of this new integration scheme was benchmarked against a more standard SADP flow. The roughness performance post mandrel formation and post spacer deposition for this new scheme is significantly improved over our standard EUV SADP baseline using a standard EUV SADP flow.

We report a sub-30-nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology targeting the back end of line metal line patterning applications for logic nodes beyond 5 nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193-nm immersion SADP targeting a 40-nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, spin on carbon, spin on glass). The multicolor integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and, more generally, edge placement error as a whole for advanced process nodes. Unbiased line edge roughness (LER)/line width roughness (LWR) analysis comparison between EUV SADP and 193-nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open, and dielectric etch compared to 193-nm immersion SADP, the final process performance is matched in terms of LWR (1.08-nm 3 sigma unbiased) and is 6% higher than 193-nm immersion SADP for average unbiased LER. Using EUV, SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.

Double patterning lithography (DPL) is the most likely manufacturing process for sub-32nm technology nodes; however, there are several double patterning strategies each of which exhibits different layout decomposition challenges. Self-aligned double patterning (SADP) has attracted much interest due to its robustness against overlay errors, but SADP compliance depends strongly on the characteristics of the individual masks generated during the layout decomposition. This work establishes SADP decomposition requirements and proposes a litho-friendly layout decomposition method. First, we explain the main parameters that limit printability of SADP decomposed layouts. In-silico experiments indicate that layout patterns which are printed by the Trim mask may experience the highest levels of image transfer sensitivity. For that reason, these patterns should be assisted by sidewalls of spacer patterns which are robustly printed. Next, we present an ILP-based decomposition method which avoids decomposition conflicts and sensitive Trim edges simultaneously. Our experiments on several industrial designs reveal that the proposed method decreases the total length of sensitive Trim patterns and consequently reduces the overall edge placement error significantly.

As the technology nodes scale down to sub-22 nm, double patterning lithography has been considered as a practical solution for layout manufacturing. Compared with litho-etch-litho-etch, self-aligned double patterning (SADP) has better overlay control. To have a better SADP layout decomposability of routing patterns, we consider SADP during detailed routing stage. Two major types of SADP processes are considered: 1) spacer-is-dielectric type and 2) spacer-is-metal type. Different from previous works, the idea of color preassignment is adopted for SADP-aware detailed routing. An elegant graph model is proposed to capture both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules in detailed routing. We apply a negotiated congestion based rip-up and reroute scheme to achieve better routability while maintaining SADP design rules. Compared with other state-of-the-art academic works, our approach does not produce any side overlay error and no SADP design rules violation is reported. Meanwhile, a better solution in terms of total wirelength, routability, and runtime is achieved.

Self-Aligned-Double-Patterning (SADP) is a potential technology for metal layers in N10 and beyond nodes. SADP manufacturing process comes with lots of challenges. Several approaches were introduced to manufacture SADP. The most major SADP manufacturing approach is the Spacer-Is-Dielectric (SID). One of the main advantages of SADP over Litho-Etch-Litho-Etch (LELE) Double Patterning (DP) is better Mask Overlay Control. In addition, SADP results in better process tolerance and lower Line-Width Roughness. In this paper, we propose a model-based manufacturing flow for SID-SADP approach. The flow includes: (1) SADP Patterns Decomposition, (2) Etch Retargeting, (3) Sub Resolution Assist Features (SRAF) Insertion, (4) Optical Proximity Correction (OPC) process, and finally (5) Verification. The motivation beyond developing this flow is to find the least number of needed masks to achieve satisfactory imaging quality, and to characterize possible challenges in each step of the flow. Consequently, we highlight the challenges and the proposed techniques we examined to meet this objective.

EUV is an ongoing industry challenge to adopt due to its current throughput limitations. The approach to improve throughput has primarily been through a significant focus on source power which has been a continuing challenge for the industry. The subject of this paper is to review and investigate the application of SADP (Self aligned double patterning) as a speed enhancing technique for EUV processing. A process with the potential of running a 16 nm self-aligned final etched pattern in less than 10mJ exposure range is proposed. Many of the current challenges with shot noise and resolution change significantly when SADP is used in conjunction with EUV. In particular, the resolution challenge for a 16nm HP final pattern type image changes to 32nm as an initial pattern requirement for the patterned CD. With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry where the relaxation of both LER and CD together combined, give the resist formulation space a new target when EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final 16nm half pitch target pattern to align with the industry needs. If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added costs associated with the double patterning process. This flow can then be shown to be an enabling approach for many EUV applications.

Among double patterning techniques, Self-aligned double patterning (SADP) has the advantage of good mask overlay control, which has made SADP a popular double patterning method for sub-32nm technology nodes. However, SADP process places several limitations on design flexibility. This work exploits an alternative post routing approach that has the flexibility to resolve lithography violations without the overhead of repeated rule checking. In addition, it allows for successive refinement in the definition of lithographic violations as the process node matures, and implementation of fixes as localized ECO (Engineering Change Order) operations without needing to reroute the complete design.

Photolithography has been a driving force behind semiconductor scaling, but the technology has been at a standstill since the development of 193-nm water-based immersion lithography. As a consequence, the double patterning process has become the standard technology for diverse types of semiconductor devices as a means of extending the life of 193-nm exposure technology. We have previously reported on the extendibility and versatility of the double patterning process, from pitch-doubling by self-aligned double patterning (SADP)[1] to pitch-quadrupling by self-aligned quadruple patterning (SAQP)[2]. We also reported on the effectiveness of SADP technology for increasing resolution in hole patterns. While waiting for the development of extreme ultraviolet (EUV) lithography tools to be completed, it will be necessary to search out possibilities for further semiconductor scaling using the double patterning process as the mainstream technique for extending the life of 193-nm immersion lithography.

Self-aligned double patterning (SADP) is being applied to 7nm technology node and below for back-end metal layers (routing layers) with pitches down to ~40nm. Unlike the traditional litho-etch-litho-etch (LELE) approach, SADP splits pitch using spacers whose 2nd pattern (Color-B) is self-aligned to its 1st pattern (Color-A). As a result, the SADP approach produces less variation than LELE approach by removing the second pattern misalignment on Si. Although SADP provides better overlay controllability than LELE, it still encounters many challenges. One of the challenges is controlling the 2nd patterning linewidth and uniformity. In general, the Color-B critical dimension (CD) has a larger variation than Color-A CD in the SADP process using Mandrel structure. In this paper, we investigate variations to the SADP Color-B CD based on self-aligned litho-etch litho-etch (SALELE) process flow, including the lithographic CD uniformity, hard mask etching, spacer etch and final Si etch. The corresponding contribution to Color-B CD variation is analyzed each step. After the major contributors to Color-B variation are identified, an experiment was designed to reduce Color-B pattern variation during the process. The silicon results show that compared with the old process condition, the new process can reduce Color-B variation significantly. With this new process, Color-B variation is comparable to Color-A variation.

The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer. This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.

Amongst the possible double patterning strategies for sub 32nm processes, self-aligned double patterning (SADP) has moved from Flash-only processes to more general purpose devices. The reason is that while litho-etch- litho-etc (LELE) process was originally preferred due to its simplicity and relative low cost, its sensitivity to overlay error has prompted the search for other methods. Although the basic SADP process is fairly robust against the overlay error, the robustness of 2D SADP method strongly depends on layout and decomposition styles and decomposability compliance. In this paper, we first discuss different printability challenges for SADP method. Afterward, we propose a SADP-aware detailed routing method, by applying a correct-by-construction approach, to provide SADP-friendly layouts. This method performs detailed routing and layout decomposition concurrently to prevent litho-limited layout configurations. Experimental results show that, compared with a SADP-blind detailed router, the proposed method achieves considerable robustness against lithography imperfection in expense of tolerable wire length overhead.

Multipatterning has enabled continued scaling of chip technology at the 28nm node and beyond. Selfaligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) as well as Litho- Etch/Litho-Etch (LELE) iterations are widely used in the semiconductor industry to enable patterning at sub 193 immersion lithography resolutions for layers such as FIN, Gate and critical Metal lines. Multipatterning requires the use of multiple masks which is costly and increases process complexity as well as edge placement error variation driven mostly by overlay. To mitigate the strict overlay requirements for advanced technology nodes (7nm and below), a self-aligned blocking integration is desirable. This integration trades off the overlay requirement for an etch selectivity requirement and enables the cut mask overlay tolerance to be relaxed from half pitch to three times half pitch. Selfalignement has become the latest trend to enable scaling and self-aligned integrations are being pursued and investigated for various critical layers such as contact, via, metal patterning. In this paper we propose and demonstrate a low cost flexible self-aligned blocking strategy for critical metal layer patterning for 7nm and beyond from mask assembly to low –K dielectric etch. The integration is based on a 40nm pitch SADP flow with 2 cut masks compatible with either cut or block integration and employs dielectric films widely used in the back end of the line. As a consequence this approach is compatible with traditional etch, deposition and cleans tools that are optimized for dielectric etches. We will review the critical steps and selectivities required to enable this integration along with bench-marking of each integration option (cut vs. block).

Through the continuous scaling with extension of 193-immersion lithography, the multi-patterning process with the grid-based design has become nominal process for fine fabrication to relax tight pitch designs^[1]. In self-aligned type multiple patterning, 7 nm node gate pattern was reported^[2],[3] and it was become a focal point LER on core-pattern is essential category to control pattern placement variations. Though CD uniformity (CDU) on line pattern in self-aligned double patterning (SADP) is relatively stable caused in high thickness controllability of spacer deposition films, the variations of CDU and LER on first core pattern impinge the CDU on space and pitch pattern. In previous study, pattern fidelity of single exposure patterning was improved through photoresist smoothing process using direct-current superposition technique^[4],[5]. In this paper, we will report that photoresist smoothing work in an efficient way to pattern fidelity control in self-aligned type multiple patterning.

As FinFET feature size scaling down, the fins are against more critical challenges by using either self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) method. Wiggling, line width roughness (LWR) and line edge roughness (LER) play more crucial roles at sub-14nm technology and beyond. Traditionally, post plasma treatment methods for photoresist are largely investigated to improve the LWR and LER. For the SADP and SAQP technology, pattern transferring is also another critical feature of dry etch process for pattern line wiggling. In this paper, both plasma photoresist treatment and dry etch process optimization are studied for improving LWR and LER.