Study of critical dimension and overlay measurement methodology using SEM image analysis for process control

In 32nm/22nm advanced technology node, double patterning lithography is considered for semiconductor manufacturing. It necessitates tightened requirement of overlay measurement, i.e. to measure the position of a pattern with respect to that of a pattern in the underlying layer. The measurement target design plays a fundamental role in overlay precision and accuracy. Typical alignment target, such as bar-in-bar or box-in-box (BIB), has precision, accuracy, and size restrictions. This prompts us to look into better alignment targets. Recently, scatterometry-based metrology and profile model capability have been extended to measure multi-level grating structures. In addition, scatterometry has been shown to be the best choice for integrated metrology to perform wafer-to-wafer control. Therefore, it makes sense to consider using scatterometry for overlay measurement. In this research, the modeling analysis is performed on the spectra taken directly from a real pattern area with grating-ongrating structure. The critical dimension (CD) at the grating on top and the lateral shift between the top and the bottom gratings can be detected simultaneously. The lateral shift between the layers can be verified with the traditional overlay box. Unlike the traditional BIB target that has micrometer CD size, the CD size of the scatterometry overlay (S_OVL) target is much closer to that on the real device. So, it can much better reflect the overlay (OVL) shift on real devices. We also studied the non-model-based S_OVL measurement using a 673-nm semiconductor laser with a 10μm x 20μm target size, wafer-to-wafer control of CD and lateral shifts on some critical layers with grating-on-grating structure, as well as the CD and OVL variations within layer and from layer to layer for double patterning.

Background: Overlay (OV) is a very important indicator for characterizing the pattern position accuracy between two layers in an integrated circuit in the manufacturing industry. The self-aligned double-patterning (SADP) process, which is limited to the resolution of deep ultraviolet lithography, is being extensively used for the volume manufacturing of integrated circuits. However, compared to the planar process, the SADP process poses new challenges for OV control.Aim: We investigate the bottom grating asymmetry of a microdiffraction-based overlay (μDBO) target in the SADP process and its effect on OV measurement.Approach: The bottom grating of the OV metrology target is analyzed through scanning electron microscopy and transmission electron microscopy. The imbalance of the −1st- and +1st-order diffraction light intensities of the asymmetrical bottom OV target is characterized. Finally, the effects of light polarization and wavelength on the OV accuracy are simulated.Results: Asymmetric behavior of bottom OV grating is identified. OV dependency on the measurement-light polarization is determined. The simulation results indicate that wavelength and polarization affect the OV accuracy simultaneously.Conclusions: We studied the bottom grating asymmetry-induced inaccuracy in DBO measurement and can assist in understanding the mechanism of measurement light-interaction with the OV grating to enhance the DBO accuracy to a new level.

Overlay (OVL) is one significant performance indicator for the lithography process control in semiconductor manufacturing. The accuracy of the OVL metrology is extremely critical for guarantee the lithography quality. Currently, diffraction-based overlay (DBO) is one of the mainstream OVL metrology techniques. Unfortunately, the accuracy of the DBO metrology is largely affected by the defect features of the OVL target. Therefore, there is a strong need to investigate the impacts of these target defects on the DBO metrology performance. However, efficiently investigating the statistical and interactive impacts of various DBO target defects remains challenging. This study aims to address this issue through proposing an intelligent sensitivity analysis approach. A cumulative distribution based global sensitivity analysis (GSA) method is utilized to assess the nonlinear influences of multiple defects in the OVL target on the DBO inaccuracy. The scenarios with both known and unknown distributions of the OVL target defects are considered. For the former, a neural network driven forward model is constructed for fast calculating the optical diffraction responses to accelerate the GSA process. For the latter, another neural network based inverse model are built for efficiently estimating the distribution of the target defects. Finally, a series of simulation experiments are conduct for typical DBO targets with multiple common defect features. The results demonstrate the effectiveness and robustness of the proposed approach as well as give valuable insights into the DBO defect analysis. Our study provides a strong tool to assist the practitioners in achieving intelligent and efficient DBO analysis and thus in enhancing OVL metrology performance.

The authors evaluated the feasibility of using coherent scattering microscopy (CSM) as an actinic metrology tool by employing it to determine the critical dimension (CD) and normalized image log-slope (NILS) values of contaminated extreme ultraviolet (EUV) masks. CSM was as effective as CD scanning electron microscopy (CD-SEM) in measuring the CD values of clean EUV masks in the case of vertical patterns (nonshadowing effect); however, only the CSM could detect shadowing effect for horizontal patterns resulting in smaller clear mask CD values. Owing to weak interaction between the low-density contaminant layer and EUV radiation, the CSM-based CD measurements were not as affected by contamination as were those made using CD-SEM. Furthermore, CSM could be used to determine the NILS values under illumination conditions corresponding to a high-volume manufacturing tool.

In semiconductor device manufacturing process, it is necessary to measure overlay error between integrated layers. As semiconductor process design rules continue to shrink, small overlay error comes to lead to the fatal fault of the device electrical property. As a result, the needs for the dense overlay measurement in the chip with the use of circuit pattern increase. We propose an automatic extraction technique of the evaluation points (EPs) that are suitable for the overlay measurement by scanning electron microscopy using design data of the device pattern layout. The proposed algorithm extracts all measureable patterns by evaluation of the positional relationship between a segment pair on the upper and lower layers by plural selection indices. Simulation was performed to estimate the overlay error distribution within the shot area using the EPs automatically extracted by the proposed method. The standard deviations of estimation errors in the x‐ and y‐directions were 0.06 nm and 0.10 nm (3ó), respectively. It was confirmed that distortion in the exposure apparatus can be estimated automatically and highly accurately.

Due to the serial pattern data transfer in electron beam lithography (EBL), there is a larger spectrum of dynamic overlay errors as compared to projection optical or extreme ultraviolet lithography. A good EBL overlay mark needs to be of high resolution, i.e., small enough size to capture the details of temporally and spatially distributed overlay error variations across a semiconductor chip. A small, one critical dimension unit or about 10–50 nm size, dot exposed in successive lithography layers is the smallest size overlay mark. This overlay mark size allows for multiple marks to be placed across the chip to measure and analyze spatial variation of the overlay errors. If the single dot is replicated into a small matrix of dots, additional overlay error information can be obtained from local variations within the matrix. Analysis of the time-dependent variations of the local overlay errors in these dot-matrix marks is useful in determining the frequency of sources of overlay errors affecting the different lithography layers.

As device size is going under the sub-60 nanometer scale, lithography is facing its resolution limit. To solve this resolution limit it has been suggested that one critical device layer could be made from multi photo/etch process, which needs tighter overlay and critical dimension (CD) controls than normal single exposure process. For CD control in this multi photo/etch process, the problem is that we do not know which pattern is made from which photo/etch process after final process. This makes it impossible to measure the specific process pattern's CD independently. In this case the conventional CD measuring method, which measures multi CDs in FOV(Field Of View) of SEM(Scanning Electronic Microscope) and control their average and distribution, couldn't know the average difference between both patterns because the variance from simply measured multi CD is just sum of each variance and their cross terms not including the average difference. In this paper it is pointed out the statistical problem of classical multi CD measurement in the indistinguishable multi-process pattern and a compensative method is suggested with a new statistical formula.

Double patterning technology is capable of extending usability of immersion ArF systems for 32nm half-pitch node and below. However, overlay errors between the two patterning steps will directly contribute to critical dimension variation in a dual litho-etch process. The overlay errors need to be reduced significantly to meet the tight critical dimension uniformity requirement in the technology nodes. The present scanners are able to correct intra- and inter-field overlay errors that include not only linear terms but also certain higher-order terms. As a result, a 3nm overlay requirement for DPT becomes feasible by applying the most advanced correction schemes. Overlay modeling with a larger number of sample fields will give a more accurate estimate of the model parameters and will therefore improve the overlay corrections; however, metrology time will increase simultaneously. To balance the correction accuracy and metrology time, the number of fields and its layout on the wafer must be optimized. This also applies to wafer alignment, one of the other factors that determine the overlay performance. A bad alignment sampling scheme will cause a poor overlay performance in the end. Increasing the number of sample fields can improve the alignment performance but wafer throughput will be impacted immediately. Performance of the intra-field correction is dependent on number and distribution of the markers within an exposure field. Correction per field, for instance, is one of the most effective correction schemes. However, it needs to measure extra markers in each field for overlay modeling especially when including high-order terms. To limit the chip area occupied by the markers and the metrology time, it is necessary to well control the number of the markers. Moreover, accuracy of the overlay models is sensitive to layout of the markers. The overlay marker layout hence needs to be optimized to gain a robust correction with a minimum number of markers. In this paper, firstly we developed various geometry-based sampling methods for both alignment and overlay corrections to evaluate correction robustness while keeping the number of sample fields as small as possible. The results show that modeling with a limited number of fields can adequately describe a full-wafer alignment/overlay signature and the errors can be well corrected accordingly. A hybrid sampling approach was then proposed taking into consideration the spatial coverage (geometry-based) as well as the overlay signature of the fields. To improve the intra-field correction, an algorithm to assist in designing the layout of the overlay markers on a mask was developed. The most effective marker layouts with the least number of markers were suggested for different correction schemes. Using the most effective correction scheme as well as the proposed optimization techniques, the overlay performance can be improved to meet the overlay requirement of the 32nm DPT.

As the optical lithography advances into the sub-30nm technology node, many candidates of the lithography have been discussed. Double pattering technology (DPT) has been a primary lithography candidate for the direct contact of the sub-30nm device due to a merit of a low mask cost and process stability compared to the extreme ultraviolet lithography (EUV). However, the major concerns of DPT are the critical dimension (CD) skew and overlay error between the 1st and 2nd pattering, which cause the degradation of electrical performance such as the mismatch of the pair transistors of the analog circuit. If we assume there is the 10nm position difference of the direct contact between the pair transistors, which is induced by the overlay error between the 1st and 2nd pattering of the DPT process, then the threshold voltage difference between the pair transistors is about 10%. Therefore, the direct contact of the pair transistors must be decomposed as the same color to minimize the threshold voltage variation of the analog circuit. Since the DPT process of the direct contact is the litho-etch-litho-etch (LELE) process, there are the CD variations induced by the global density difference between the 1st and 2nd mask. In this paper, we newly develop the DPT methodology to decompose the direct contact of the pair transistors to the same mask using the optimized marking polygons, decomposition algorithm. In addition, the decomposition algorithm for the density balancing between the 1st and 2nd mask is developed to minimize the CD variations caused by the density difference. Our main contributions are as follows. (1) The optimal marking polygons, which group the direct contacts of the pair transistors, are designed to consider the layout configurations of pair transistors. The space between each contact located on the same marking polygon is designed to be larger than the resolution limit of the single exposure, so that the contacts grouped by the same marking polygon can be decomposed as the same color. (2) The whole contacts grouped by the same marking polygon are changed to the representative single contact, and then the colors of the grouped contacts are assigned by the representative single contact and its surrounded contacts. (3) After decomposing the layout to consider the contact on the pair transistors, the remaining contacts, which is not necessary to decompose from the view point of the patterning limit, are decomposed to satisfy the density balance between the 1st and 2nd mask. Consequently, we can achieve the pattering margin and electrical performance of sub-30nm device by applying the new DPT methodology to the direct contact.

Double patterning technology overlay errors result in critical dimension (CD) distortions, and CD nonuniformity leads to overlay errors, demanding increased critical dimension uniformity (CDU) and improved overlay control. Scatterometry techniques are used to characterize the CD uniformity, focus, and dose control. We present CDU and profile characterization for spacer double patterning structures by advanced scatterometry methods. Our results include normal incidence spectroscopic reflectometry (NISR) and spectroscopic ellipsometry (SE) characterization of CDU sensitivity in spacer double patterning stacks. We further show the results of spacer DP structures by NISR and SE measurements. Metrology comparisons at various process steps including litho, etch, and spacer, and validation of CDU and profile, are all benchmarked against traditional critical dimension scanning electron microscope measurements.

The Hitachi Model S-6280 high resolution field emission Scanning Electron Microscope (SEM) is used at Motorola's MOS-12 facility for Critical Dimension (CD) measurements of less than 1 micrometer in size. This tool is used to measure 200-mm diameter wafers with a low accelerating voltage in the range 0.7-1.0 kV. During new process development the tool is run in both manual mode and in a fully automated mode utilizing patten recognition for global alignment as well as feature CD measurement. Results on the reproducibility of fully- automated measurements show that this technique provides a significantly improved measurement capability compared to the standard manual technique.

Traditionally, lithography critical dimension (CD) measurements with stepper de-focus and deltas in sidewall angle do not correlate well with the ultimate product measurement, namely electrical performance. It is important in etch bias control, therefore, to control more than just the physical CD. It is at a minimum, important to show how the changes in sidewall angle control at lithography relate to etch biases. This is especially important as chip geometries shrink, and the size and shape of the sidewall becomes a larger portion of the line width geometry. This makes precise CD measurements coupled with slope angle measurements, in real time, important to process control in lithography so that ultimately the desired dimension is achieved at the post etch step, and therefore electrical performance can be gauged. We will present data taken from Focus/Exposure Matrices in the form of CD measurements, in-line sidewall angle reconstruction, and electrical measurements. We hope to correlate electrical performance to post develop CD and slope sidewall angle as measured without destructive cross sections.

The use of optical metrology techniques in process control for microelectronic manufacturing has become widespread. These techniques are fast and non-destructive, allowing a higher sampling rate than non-optical methods like scanning electron or atomic force microscopy. One drawback of most optical metrology tools is the requirement that special measurement structures be fabricated in the scribe line between chips. This poses significant limitations regarding the characterization of lithography processes that may be overcome via in-chip measurements. In this paper we present experimental results for an in-chip optical metrology technique that allows direct measurement of both critical dimensions and overlay displacement errors in the DRAM manufacturing process. This technique does not require special target structures and is performed on the actual semiconductor devices.

As the essential techniques for the CD (Critical Dimension) measurement of the LCD pattern, there are various modules such as an optics design, auto-focus [1-4], and precise edge detection. Since the operation of image enhancement to improve the CD measurement repeatability, a ring type of the reflected lighting optics is devised. It has a simpler structure than the transmission light optics, but it delivers the same output. The edge detection is the most essential function of the CD measurements. The CD measurement is a vital inspection for LCDs [5-6] and semiconductors [7-8] to improve the production yield rate, there are numbers of techniques to measure the CD. So in this study, a new subpixel algorithm is developed through facet modeling, which complements the previous sub-pixel edge detection algorithm. Currently this CD measurement system is being used in LCD manufacturing systems for repeatability of less than 30 nm.

In semiconductor device manufacturing, critical dimension (CD) metrology provides a measurement for precise line-width control during the lithographic process. Currently scanning electron microscope (SEM) tools are typically used for this measurement, because the resolution requirements for the CD measurements are outside the range of optical microscopes. While CD has been a good feedback control for the lithographic process, line-widths continue to shrink and a more precise measurement of the printed lines is needed. With decreasing line widths, the entire sidewall structure must be monitored for precise process control. Sidewall structure is typically acquired by performing a destructive cross sectioning of the device, which is then imaged with a SEM tool. Since cross sectioning is destructive and slow, this is an undesirable method for testing product wafers and only a small sampling of the wafers can be tested. We have developed a technique in which historical cross section/top down image pairs are used to predict sidewall shape from top down SEM images. Features extracted from a new top down SEM image are used to locate similar top downs within the historical database and the corresponding cross sections in the database are combined to create a sidewall estimate for the new top down. Testing with field test data has shown the feasibility of this approach and that it will allow CD SEM tools to provide cross section estimates with no change in hardware or complex modeling.