Statistical analysis of CD-SEM measurement and process control in the indistinguishable multi-process patterns

Traditionally, lithography critical dimension (CD) measurements with stepper de-focus and deltas in sidewall angle do not correlate well with the ultimate product measurement, namely electrical performance. It is important in etch bias control, therefore, to control more than just the physical CD. It is at a minimum, important to show how the changes in sidewall angle control at lithography relate to etch biases. This is especially important as chip geometries shrink, and the size and shape of the sidewall becomes a larger portion of the line width geometry. This makes precise CD measurements coupled with slope angle measurements, in real time, important to process control in lithography so that ultimately the desired dimension is achieved at the post etch step, and therefore electrical performance can be gauged. We will present data taken from Focus/Exposure Matrices in the form of CD measurements, in-line sidewall angle reconstruction, and electrical measurements. We hope to correlate electrical performance to post develop CD and slope sidewall angle as measured without destructive cross sections.

The Hitachi Model S-6280 high resolution field emission Scanning Electron Microscope (SEM) is used at Motorola's MOS-12 facility for Critical Dimension (CD) measurements of less than 1 micrometer in size. This tool is used to measure 200-mm diameter wafers with a low accelerating voltage in the range 0.7-1.0 kV. During new process development the tool is run in both manual mode and in a fully automated mode utilizing patten recognition for global alignment as well as feature CD measurement. Results on the reproducibility of fully- automated measurements show that this technique provides a significantly improved measurement capability compared to the standard manual technique.

As the essential techniques for the CD (Critical Dimension) measurement of the LCD pattern, there are various modules such as an optics design, auto-focus [1-4], and precise edge detection. Since the operation of image enhancement to improve the CD measurement repeatability, a ring type of the reflected lighting optics is devised. It has a simpler structure than the transmission light optics, but it delivers the same output. The edge detection is the most essential function of the CD measurements. The CD measurement is a vital inspection for LCDs [5-6] and semiconductors [7-8] to improve the production yield rate, there are numbers of techniques to measure the CD. So in this study, a new subpixel algorithm is developed through facet modeling, which complements the previous sub-pixel edge detection algorithm. Currently this CD measurement system is being used in LCD manufacturing systems for repeatability of less than 30 nm.

In recent years, mask critical dimension (CD) linearity and uniformity has become increasingly important. The ITRS roadmap shows the mask CD control requirements exceeding those of the wafer side beyond the 45nm node. Measurements show that there are systematic, uncorrected proximity effects even when a state-of-the-art proximity effect correction (PEC) algorithm is used. The uncorrected proximity effect is predictable with a computational model. The model for e-beam lithography and etch process contains terms to model short-range pattern density effects and plasma shadowing effect in Cr-etch. The model is calibrated using CD measurements on a test mask. The model is valid for arbitrary 2-D patterns. We present a model-based mask process compensation (MPC) method which applies geometric changes to polygons as in OPC. We discuss the goodness of model fit to the calibration data; verification of the calibrated model by SEM images; and the improvement obtained by MPC. The mask writing error, i.e. final inspection CD minus incoming database CD, was reduced by a factor of 2 through the use of MPC.

The dispositioning of mask defects must also heed the increasing gap between the lithography wavelength and wafer-feature widths. For the larger technology nodes, where printed-wafer shapes are similar to those on the mask, mask-level analysis is sufficient. However, for smaller nodes, wafer-level scoring is useful since every defect does not significantly impact the wafer. Wafer-level analysis often relies on measurements of critical dimension (CD). However, as reticle enhancement technology proliferates, there are increasingly more curved edges where CD cannot be used. For example, false alarms can result from measuring CD near line ends because slight variations in measurement position may produce large CD changes. More importantly, a killer defect may be missed if cutlines are forbidden near line ends because the CD measurements are too far from the defect. Wherever CD measurements are not advisable, we advocate the use of Area scoring by computing the difference in printed feature area. We are not abandoning CD scoring but rather combining it with Area scoring, and using the more pessimistic score. For Area scoring, we use (Defect area - Reference area)/(Reference area). In general, the reference area is difficult to define since many shapes are not easily parsed into primitive shapes. Therefore, we use a square of side equal to the target CD. This square defines the window for a sliding-window average of the area difference. The maximum average value is then chosen from the entire image. Unlike Edge Placement Error, Area is sensitive to long, thin difference regions. Unlike Flux or Maximum Intensity Difference, Area is threshold-aware; it measures what prints and shows process-window variation.

In this paper the bias table models for the wafer scale SmartNIL™ technology are addressed and validated using complete Scanning Electron Microscopy (SEM) characterizations and polynomial interpolation functions. Like the other nanoimprint lithography (NIL) technics, this replication technology is known to induce Critical Dimension (CD) variations between the master and the imprint, due to polymer shrinkage, soft stamp deformation or thermal expansion. The bias between the former and final object follows peculiar rules which are specific to this process. To emphasis these singularities, Critical Dimension (CD) uniformity analyses were analyzed onto 200 mm wafers imprinted with the HERCULES® NIL equipment platform. Dedicated masters were manufactured to capture the process signatures: horizontal and vertical line arrays, local densities ranging from 0.1 to 0.9 and minimum CD of 250 nm. The silicon masters were manufactured with 248 optical lithography and dry etching and treated with an anti-sticking layer from Arkema. CD measurements were made for the master and the replicates on 48 well selected features to build interpolations. The bias table, modelled by polynomial functions with a degree of 5 for the density and a degree of 3 for the CD, are compared between horizontal and vertical features, and between the center and the edge of the wafers. Finally the focus is made on the validation of the interpolations by comparing the computed bias and the experimental data.

Introduction and problem statement Given that EUV lithography allows printing smaller Critical Dimension (CD) features, it can result in non-normal distributed CD populations on ADI wafers [Civay SPIE AL 2014], leading to errors in predicted failure rates [Bristol SPIE AL 2017]. As a result, there is a need to quantify the actual behavior of the CD population extremes by means of massive metrology [Dillen EUVL 2018]. Not only allows this to study the CD distribution, we can in parallel also evaluate pattern quality and the failure mechanisms leading to defects. This massive metrology method provides an accurate failure rate based on CD, and enables new possibilities to define a failure rate based on different metrics in a single measurement. Method We analyze the CD uniformity of pillars in polar coordinates using a global waveform based thresholding strategy. In conjunction with this CD information, we also evaluated the print quality of each individual measured feature. Fig 1. In line detected anomalies and failure definitions As we gather this information during the measurement of CD, we can limit the additional measurement overhead to neglectable levels. Application and outlook We will show how we can leverage this to determine a defect based process window and relations of failure mechanisms through process conditions (see figure 2). When we take failures in a CH dataset into account, we illustrate the effect on the shape of a large dataset distribution in figure 3. Fig 2. Defect identification for a through exposure dose experiment of pillars. For each condition >13k pillars where measured. The plot clearly shows an asymmetric behavior due to different failure mechanisms at low and high energy. The 2 vertical lines at relative energies 0.93 and 1.05 times nominal indicate the low defect process window. Fig 3. A distribution of measured regular grid dense CH. The red line is the unfiltered CD data, the blue line is the shape of the distribution after filtering individual CH measurements that have a much lower contrast than expected.

In semiconductor device manufacturing, critical dimension (CD) metrology provides a measurement for precise line-width control during the lithographic process. Currently scanning electron microscope (SEM) tools are typically used for this measurement, because the resolution requirements for the CD measurements are outside the range of optical microscopes. While CD has been a good feedback control for the lithographic process, line-widths continue to shrink and a more precise measurement of the printed lines is needed. With decreasing line widths, the entire sidewall structure must be monitored for precise process control. Sidewall structure is typically acquired by performing a destructive cross sectioning of the device, which is then imaged with a SEM tool. Since cross sectioning is destructive and slow, this is an undesirable method for testing product wafers and only a small sampling of the wafers can be tested. We have developed a technique in which historical cross section/top down image pairs are used to predict sidewall shape from top down SEM images. Features extracted from a new top down SEM image are used to locate similar top downs within the historical database and the corresponding cross sections in the database are combined to create a sidewall estimate for the new top down. Testing with field test data has shown the feasibility of this approach and that it will allow CD SEM tools to provide cross section estimates with no change in hardware or complex modeling.

A procedure for calibrating a resist model iteratively adjusts appropriate parameters until the simulations of the model match the experimental data. The tunable parameters may include the shape of the illuminator, the geometry and transmittance/phase of the mask, light source and scanner-related parameters that affect imaging quality, resist process control and most importantly the physical/chemical factors in the resist model. The resist model can be accurately calibrated by measuring critical dimensions (CD) of a focus-exposure matrix (FEM) and the technique has been demonstrated to be very successful in predicting lithographic performance. However, resist model calibration is more challenging in the low k1 (<0.3) regime because numerous uncertainties, such as mask and resist CD metrology errors, are becoming too large to be ignored. This study demonstrates a resist model calibration procedure for a 0.29 k1 process using a 6% halftone mask containing 2D brickwall patterns. The influence of different scanning electron microscopes (SEM) and their wafer metrology signal analysis algorithms on the accuracy of the resist model is evaluated. As an example of the metrology issue of the resist pattern, the treatment of a sidewall angle is demonstrated for the resist line ends where the contrast is relatively low. Additionally, the mask optical proximity correction (OPC) and corner rounding are considered in the calibration procedure that is based on captured SEM images. Accordingly, the average root-mean-square (RMS) error, which is the difference between simulated and experimental CDs, can be improved by considering the metrological issues. Moreover, a weighting method and a measured CD tolerance are proposed to handle the different CD variations of the various edge points of the wafer resist pattern. After the weighting method is implemented and the CD selection criteria applied, the RMS error can be further suppressed. Therefore, the resist CD and process window can be confidently evaluated using the accurately calibrated resist model. One of the examples simulates the sensitivity of the mask pattern error, which is helpful to specify the mask CD control.

Due to the rapidly reduced imaging process windows and increasingly stingent device overlay requirements, sub-130 nm lithography processes are more severely impacted than ever by systamic fault. Limits on critical dimensions (CD) and overlay capability further challenge the operational effectiveness of a mix-and-match environment using multiple lithography tools, as such mode additionally consumes the available error budgets. Therefore, a focus on advanced process control (APC) methodologies is key to gaining control in the lithographic modules for critical device levels, which in turn translates to accelerated yield learning, achieving time-to-market lead, and ultimately a higher return on investment. This paper describes the implementation and unique challenges of a closed-loop CD and overlay control solution in high voume manufacturing of leading edge devices. A particular emphasis has been placed on developing a flexible APC application capable of managing a wide range of control aspects such as process and tool drifts, single and multiple lot excursions, referential overlay control, 'special lot' handling, advanced model hierarchy, and automatic model seeding. Specific integration cases, including the multiple-reticle complementary phase shift lithography process, are discussed. A continuous improvement in the overlay and CD Cpk performance as well as the rework rate has been observed through the implementation of this system, and the results are studied.

As the design rule of semiconductor devices shrinks to below 100nm dimensions, the degree of pattern alignment from different process levels has become a crucial factor affecting both process control and induced defect on unit process. Isolated and dense patterns were formed at process layers from front-end through to back-end on wafers using sub 100nm device process utilizing ArF lithography under various lithography conditions. As pattern size is reduced, overlay discrepancies become larger. The OL (overlay) error is very important because the pattern misalignment induces critical defects for the device. For many years, overlay metrology for process control has been measured by 4-corner box-in-box methods in chip. OL errors and CD (Critical Dimension) values have been measured on different tool. CD values have been measured on SEMs (Scanning Electron Microscope) and OL errors have been measured on optical tools. The accuracy of OL error metrology is limited by the resolution of tool, which is on the order of 1&#956;m. In this paper we calculated the degree of overlay errors (current level to prior level errors) through a process patterns images obtained from a CD-SEM.

The advent of integrated metrology (IM) for lithography critical dimension (CD) control has been widely discussed and debated. A number of factors are pushing chip makers in the direction of IM implementation, including shrinking line widths and decreasing CD budgets, higher throughput Litho cells, escalating cost and impracticality of stand-alone CD metrology, and reducing overhead (or non value-add) time. These factors combine to make the question of IM for CD control "when" rather than "if". Scatterometry can provide a wealth of information about structures on a wafer including CD, sidewall angle, and film thickness for various layers. Although this information unquestioningly provides additional insight into the lithography process, in the end, the rate of IM implementation depends on its return on investment (ROI). In this paper, we discuss the implementation of integrated Optical Digital Profiling (iODPTM) on an advanced lithography track (Tokyo Electron CLEAN TRACK LITHIUSTM). Included are discussions of lithography trends, metrology requirements, and IM data flow and analysis. Various strategies for IM implementation are presented along with their associated ROIs.

OPC (Optical Proximity Correction) improves the feature CD (critical dimension) uniformity and pattern fidelity in general. However, since model calibration only takes CD measurements at optimum exposure dose and best focus condition, the correction result may not be desirable at non-optimum conditions due to significant sub-resolution process distortion. Certain specific patterns are prone to bridging or pinching (we refer this type of location as hotspot in this paper) when process drifts a little from optimum condition. Simulation based full-chip verification became the method of choice for capturing hotspots on post-OPC layouts prior to mask tape-out to save development time and cost. In this paper, a complete simulation and analysis flow using SiVL was experimented to capture hotspots for a 100nm node process. Calibrated process model and multiple optical models with different focus/threshold conditions were applied for simulation. The method and effectiveness of filtering and analyzing fatal errors from output error database was discussed. The analysis results were then correlated to actual wafer printing. A good match between prediction and experiment was found.

As the design rule of lithography becomes smaller, accuracy and precision in Critical Dimension (CD) and controllability of pattern-shape are required in semiconductor production. Critical Dimension Scanning Electron Microscope (CD SEM) is an essential tool to confirm the quality of the mask such as CD control, CD uniformity and CD mean to target (MTT). Unfortunately, in the case of extremely rounded region of arbitrary enclosed patterns, CD fluctuation depending on Region of Interest (ROI) is very serious problem in Mask CD control, so that it decreases the yield. In order to overcome this situation, we have been developing 2-dimensonal (2D) method with system makers and comparing CD performance between mask and wafer using enclosed arbitrary patterns. In this paper, we summarized the results of our evaluation that compare error budget between 1-dimensonal (1D) and 2D data using CD SEM and other optical metrology systems.

The accuracy of critical dimension measurements in scanning electron microscopes