Massive metrology and failure identification for DRAM applications (Conference Presentation)

Process windows based on Mean CD ("Critical Dimension") have been an analysis workhorse for estimating and comparing the robustness of semiconductor microlithography processes for more than 30 years. While tolerances for variation of CD are decreasing in step with the target CD, the acceptable number of printed defects has remained flat (Hint: Zero) even as the number of features increases quadratically. This disconnect between two key process estimators, CD variability and defect rate, must be addressed. At nodes that require EUV lithography, estimating the printed defects based solely on a Mean CD process window is no longer predictive. The variability / distribution of the printed CDs must be engineered so that there are no failures amongst the billions of instances, rendering the Mean CD, often measured on just hundreds or thousands of instances, a poor predictor for outliers. A "defect-aware" process window, where the count of printed defects is considered in combination with more advanced statistical analysis of measured CD distributions can provide the needed predictability to determine whether a process is capable of sufficient robustness. Determining process robustness where stochastics and defects are taken into account can be simplified by determining the CD process margin. In this work we study dense via/contact hole arrays exposed with 0.33NA single exposure EUV lithography after both the lithography and etch steps. We describe a methodology for expanding the analysis of process windows to include more than the mean and 3σ of the data. We consider the skew and kurtosis of the distribution of measured CD results per focus-exposure condition and compare/correlate the measured CD process window results to the CD process margin.

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

Traditionally, lithography critical dimension (CD) measurements with stepper de-focus and deltas in sidewall angle do not correlate well with the ultimate product measurement, namely electrical performance. It is important in etch bias control, therefore, to control more than just the physical CD. It is at a minimum, important to show how the changes in sidewall angle control at lithography relate to etch biases. This is especially important as chip geometries shrink, and the size and shape of the sidewall becomes a larger portion of the line width geometry. This makes precise CD measurements coupled with slope angle measurements, in real time, important to process control in lithography so that ultimately the desired dimension is achieved at the post etch step, and therefore electrical performance can be gauged. We will present data taken from Focus/Exposure Matrices in the form of CD measurements, in-line sidewall angle reconstruction, and electrical measurements. We hope to correlate electrical performance to post develop CD and slope sidewall angle as measured without destructive cross sections.

As the essential techniques for the CD (Critical Dimension) measurement of the LCD pattern, there are various modules such as an optics design, auto-focus [1-4], and precise edge detection. Since the operation of image enhancement to improve the CD measurement repeatability, a ring type of the reflected lighting optics is devised. It has a simpler structure than the transmission light optics, but it delivers the same output. The edge detection is the most essential function of the CD measurements. The CD measurement is a vital inspection for LCDs [5-6] and semiconductors [7-8] to improve the production yield rate, there are numbers of techniques to measure the CD. So in this study, a new subpixel algorithm is developed through facet modeling, which complements the previous sub-pixel edge detection algorithm. Currently this CD measurement system is being used in LCD manufacturing systems for repeatability of less than 30 nm.

The dispositioning of mask defects must also heed the increasing gap between the lithography wavelength and wafer-feature widths. For the larger technology nodes, where printed-wafer shapes are similar to those on the mask, mask-level analysis is sufficient. However, for smaller nodes, wafer-level scoring is useful since every defect does not significantly impact the wafer. Wafer-level analysis often relies on measurements of critical dimension (CD). However, as reticle enhancement technology proliferates, there are increasingly more curved edges where CD cannot be used. For example, false alarms can result from measuring CD near line ends because slight variations in measurement position may produce large CD changes. More importantly, a killer defect may be missed if cutlines are forbidden near line ends because the CD measurements are too far from the defect. Wherever CD measurements are not advisable, we advocate the use of Area scoring by computing the difference in printed feature area. We are not abandoning CD scoring but rather combining it with Area scoring, and using the more pessimistic score. For Area scoring, we use (Defect area - Reference area)/(Reference area). In general, the reference area is difficult to define since many shapes are not easily parsed into primitive shapes. Therefore, we use a square of side equal to the target CD. This square defines the window for a sliding-window average of the area difference. The maximum average value is then chosen from the entire image. Unlike Edge Placement Error, Area is sensitive to long, thin difference regions. Unlike Flux or Maximum Intensity Difference, Area is threshold-aware; it measures what prints and shows process-window variation.

Implementation of extreme ultra violet lithography (EUVL) for printing features of dimensions around 32nm and below has faced multiple challenges that have been overcome mostly through tool and process engineering. Currently, the main concern for implementation of EUVL in high volume manufacturing is related to stochastic defects, such as line bridges or breaks, which may occur randomly and have an impact on device performance.1 Photon shot noise, in addition to the inherent process variability and material non-homogeneities can lead to defects on the final patterned structures. As the pitch and critical dimension (CD) approach 32nm pitch and below, the dependency of stochastics defects increases exponentially. This paper fits within imec’s EUV stochastics and defectivity program, which investigates the key parameters for the generation and mitigation of defects from both a theoretical and practical approach. Initially, a reference process has been established and a methodology has been developed to capture and characterize bridge-type defects after pattern transfer into relevant layers for metrology and applications. Optical inspection and scanning electron microscopy (SEM) review are used to collect information on the number and types of defects present over large patterned areas (in the order of cm2). With a well-defined inspection technique, experiments related to fundamentals as well as materials and processes are continuously run. In the past years, imec has been leading the fundamental work on stochastic defects.2,3 De Bisschop et al. identified the “defect cliff”, or the exponential dependency of defect density as a function of space CD for multiple parameters, such as resist formulation and exposure/imaging conditions. More recently, the focus has changed to the investigation of the “defect floor”, which as the name suggests, is a flat response of defects to CD. The defect floor suggests that defectivity cannot be further improved, making one of the most relevant problems to solve for implementation of EUV in high volume manufacturing (HVM). Our results show a decomposition of the potential contributors to explore the effect of processing conditions related to scanner, track and pattern transfer on final defect density for a chemically amplified resist and attempt a comparison to a metal-oxide resist. Goal is to understand the contributors to the defect floor and identify an effective route to avoid/minimize defect formation.

The Hitachi Model S-6280 high resolution field emission Scanning Electron Microscope (SEM) is used at Motorola's MOS-12 facility for Critical Dimension (CD) measurements of less than 1 micrometer in size. This tool is used to measure 200-mm diameter wafers with a low accelerating voltage in the range 0.7-1.0 kV. During new process development the tool is run in both manual mode and in a fully automated mode utilizing patten recognition for global alignment as well as feature CD measurement. Results on the reproducibility of fully- automated measurements show that this technique provides a significantly improved measurement capability compared to the standard manual technique.

As device size is going under the sub-60 nanometer scale, lithography is facing its resolution limit. To solve this resolution limit it has been suggested that one critical device layer could be made from multi photo/etch process, which needs tighter overlay and critical dimension (CD) controls than normal single exposure process. For CD control in this multi photo/etch process, the problem is that we do not know which pattern is made from which photo/etch process after final process. This makes it impossible to measure the specific process pattern's CD independently. In this case the conventional CD measuring method, which measures multi CDs in FOV(Field Of View) of SEM(Scanning Electronic Microscope) and control their average and distribution, couldn't know the average difference between both patterns because the variance from simply measured multi CD is just sum of each variance and their cross terms not including the average difference. In this paper it is pointed out the statistical problem of classical multi CD measurement in the indistinguishable multi-process pattern and a compensative method is suggested with a new statistical formula.

In this paper the bias table models for the wafer scale SmartNIL™ technology are addressed and validated using complete Scanning Electron Microscopy (SEM) characterizations and polynomial interpolation functions. Like the other nanoimprint lithography (NIL) technics, this replication technology is known to induce Critical Dimension (CD) variations between the master and the imprint, due to polymer shrinkage, soft stamp deformation or thermal expansion. The bias between the former and final object follows peculiar rules which are specific to this process. To emphasis these singularities, Critical Dimension (CD) uniformity analyses were analyzed onto 200 mm wafers imprinted with the HERCULES® NIL equipment platform. Dedicated masters were manufactured to capture the process signatures: horizontal and vertical line arrays, local densities ranging from 0.1 to 0.9 and minimum CD of 250 nm. The silicon masters were manufactured with 248 optical lithography and dry etching and treated with an anti-sticking layer from Arkema. CD measurements were made for the master and the replicates on 48 well selected features to build interpolations. The bias table, modelled by polynomial functions with a degree of 5 for the density and a degree of 3 for the CD, are compared between horizontal and vertical features, and between the center and the edge of the wafers. Finally the focus is made on the validation of the interpolations by comparing the computed bias and the experimental data.

In recent years, mask critical dimension (CD) linearity and uniformity has become increasingly important. The ITRS roadmap shows the mask CD control requirements exceeding those of the wafer side beyond the 45nm node. Measurements show that there are systematic, uncorrected proximity effects even when a state-of-the-art proximity effect correction (PEC) algorithm is used. The uncorrected proximity effect is predictable with a computational model. The model for e-beam lithography and etch process contains terms to model short-range pattern density effects and plasma shadowing effect in Cr-etch. The model is calibrated using CD measurements on a test mask. The model is valid for arbitrary 2-D patterns. We present a model-based mask process compensation (MPC) method which applies geometric changes to polygons as in OPC. We discuss the goodness of model fit to the calibration data; verification of the calibrated model by SEM images; and the improvement obtained by MPC. The mask writing error, i.e. final inspection CD minus incoming database CD, was reduced by a factor of 2 through the use of MPC.

Extreme ultraviolet lithography (EUVL) is getting closer to practical use for mass production every year. For applying EUV lithography to manufacturing, productivity improvement is a critical challenge. Throughput and yield are important factors for productivity. EUV source power is steadily advancing year by year, bringing improvements in throughput. Furthermore, yield improvement is necessary for productivity enhancement. In order to improve the yield in EUV lithography processing, further improvement of defectivity and critical dimension (CD) uniformity is required. Reduction of residue and in-film particle defects is very crucial work to enhance the productivity. For residue defects, it is found that the residue defects detected after development inspection (ADI) are perfectly transferred to after etching inspection (AEI), meaning that high defectivity of residue deteriorates yield directly. Furthermore, in-film particle defect counts increase from ADI to AEI because particles included in spin-on-carbon (SOC) and spin-on-glass (SOG) as well as that in resist film are the sources of defects in AEI, while particles mainly included in resist film can be observed in ADI. Figure 1 shows the normalized defectivity comparison between conventional rinse and filtration used and optimizing rinse used and improving filtration efficiency in ADI and AEI. ADI defectivity in which optimized rinse is applied and improving filtration efficiency achieved 0.04, while that in which conventional rinse and filtration are used defined 1.00, meaning the 96 % of improvement. In addition, AEI defectivity by using optimized rinse and improving of filtration efficiency shows 86 % of reduction as compared with that using conventional rinse and filtration. These results reveal that our novel actions for rinse and material supply show excellent performance for defect reduction. For the other aspect of yield improvement, CD uniformity control is one of the crucial factors. CD variations are comprised of several components such as wafer to wafer CD uniformity, field to field CD uniformity. To achieve CD uniformity target for manufacturing, we have optimized developing process with the latest technology. Then, 15 % of field to field CD uniformity improvement and significant improvement of wafer to wafer CD uniformity are achieved.

Influence of MEEF change on the mask shadowing effect in extreme ultraviolet lithography

Lack of precision and accuracy of in-process critical dimension (CD) measurements of linewidth continues to be a serious problem at micrometer and submicrometer dimensions. Even with highly repeatable optical linewidth measurement systems, variable "offsets" or errors have been shown to occur with changes in process variables such as thickness of the patterned layer and sublayers and changes in the indices of refraction of the materials. All of these variations result in changes in the optical phase difference which occurs on reflection at the line edge and, therefore, results in changes in the structure of the optical image. Although an accurate coherent optical edge detection method has been developed, it requires accurate knowledge of the phase difference which is not always possible in CD measurements. This paper proposes a new dual-threshold method for edge detection and focusing, based on image theory, which can be adapted to most optical microscope-based measurement systems. It does not require knowledge of the phase difference at the line edge. The accuracy of this criterion is compared to two more widely used criteria, (1) the minimum and (2) 50% threshold, and it is concluded that, when the phase difference is unknown and varies with normal processing, the new dual-threshold method is the superior method.

A procedure for calibrating a resist model iteratively adjusts appropriate parameters until the simulations of the model match the experimental data. The tunable parameters may include the shape of the illuminator, the geometry and transmittance/phase of the mask, light source and scanner-related parameters that affect imaging quality, resist process control and most importantly the physical/chemical factors in the resist model. The resist model can be accurately calibrated by measuring critical dimensions (CD) of a focus-exposure matrix (FEM) and the technique has been demonstrated to be very successful in predicting lithographic performance. However, resist model calibration is more challenging in the low k1 (<0.3) regime because numerous uncertainties, such as mask and resist CD metrology errors, are becoming too large to be ignored. This study demonstrates a resist model calibration procedure for a 0.29 k1 process using a 6% halftone mask containing 2D brickwall patterns. The influence of different scanning electron microscopes (SEM) and their wafer metrology signal analysis algorithms on the accuracy of the resist model is evaluated. As an example of the metrology issue of the resist pattern, the treatment of a sidewall angle is demonstrated for the resist line ends where the contrast is relatively low. Additionally, the mask optical proximity correction (OPC) and corner rounding are considered in the calibration procedure that is based on captured SEM images. Accordingly, the average root-mean-square (RMS) error, which is the difference between simulated and experimental CDs, can be improved by considering the metrological issues. Moreover, a weighting method and a measured CD tolerance are proposed to handle the different CD variations of the various edge points of the wafer resist pattern. After the weighting method is implemented and the CD selection criteria applied, the RMS error can be further suppressed. Therefore, the resist CD and process window can be confidently evaluated using the accurately calibrated resist model. One of the examples simulates the sensitivity of the mask pattern error, which is helpful to specify the mask CD control.

Extreme ultraviolet lithography (EUVL) is one of the leading candidates for the next generation lithography. As the requirement on critical dimension (CD) and side wall profile control becomes ever stringent as minimum feature sizes keep shrinking following the Semiconductor Industry Association (SIA) roadmap, the patterning of the EUV mask absorber material, cost of ownership (COO) of mask, and the capability for defect free EUV masks become the crucial path in enabling the overall success of EUV lithography. The purpose of this study is to understand the etch characteristics in TaN-based EUV mask absorber etch, which will enable us to determine robust process condition in terms of CD performance and profile control. In this paper, CD bias performance in TaN-based EUV mask absorber etching is investigated within inductively coupled plasma (ICP) of fluorine-containing and chlorine-containing gas chemistries. The effects of etch parameters, such as plasma source power, bias power, and pressure, on the CD bias are evaluated through design of experiments (DOE). Some other etching characteristics like etch rate and selectivity are also correlated to the CD performance and etch profile to understand the basic etch mechanism in TaN etch. Latest etch results of the TaN-based absorber are also presented.