Study of Alignment & Overlay Strategy in 14 nm Lithography Process

Overlay performance has been a critical factor for advanced semiconductor manufacturing for years. Over time these requirements become more stringent as design rules shrink. Overlay mark design and selection are the first two steps of overlay control, and it is known that different overlay mark designs will have different responses to process conditions. An overlay mark optimized for traditional process might not be suitable for SADP (self-aligned double patterning) technology due to changes in lithography and etching process conditions. For instance, the traditional BIB (box-in-box) target defined by the core mask becomes a template structure in SADP flow, the pitch and cycle of the overlay mark is further changed after spacer formation and core film removal hence the mark recognition and robustness have been challenging for the subsequent process layers. The comprehensive study on the methodology of overlay mark design and selection is still not available for SADP process. In this paper, various types of overlay marks were designed to comply with the SADP process to get rid of the weaknesses of traditional targets. TMU (total measurement uncertainty) performance was adopted to determine the optimal overlay marks for meeting production overlay control requirements in SADP process flow. The results have suggested the segmented marks outperform to non-segmented marks on image contrast as well as TMU.

The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer. This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.

Design shrinking beyond the resolution limits of 193 nm optical lithography requires the introduction of double patterning technology (DPT) for the semiconductor industry. Two consecutive lithography and etching process (LELE; Litho-Etch-Litho-Etch) and self aligned double patterning (SADP) process are major two options of DPT.In LELE process, layout patterns are decomposed into two groups and each group is placed on a photo mask. The original layout is reconstructed on a wafer through two lithography with two those photo masks. The two lithography processes are independent because of the intermediate process in between, such as etching and resist freeze. Lithography conditions for each mask are optimized on source mask optimization (SMO) technique to enlarge lithography margin. Conventional SMO technique can be applied to the decomposed patterns since two lithography processes have no interaction as discussed above.In SADP process, a layout is also decomposed into two groups as same as the methodology for LELE process. Either decomposed group is transferred on a wafer, which is named as mandrel. Sidewalls are deposited on the mandrel patterns and the following processes such as etching and mandrel removal reconstruct the original layout.Design rules for DPT consist of two parts. One is for an original layout which is drawn by designers. The other is for each decomposed layout printed by a lithography process. Both design rules have interactions because the original layout which follows the former design rules is decomposed into two groups which follow the latter design rules.In this paper, we will discuss the relation between the two rules above. Furthermore, we will discuss the situation on triple or quadruple patterning.

New alignment mark designs in single patterning and self-aligned double patterning

Self-aligned double patterning (SADP) is being applied to 7nm technology node and below for back-end metal layers (routing layers) with pitches down to ~40nm. Unlike the traditional litho-etch-litho-etch (LELE) approach, SADP splits pitch using spacers whose 2nd pattern (Color-B) is self-aligned to its 1st pattern (Color-A). As a result, the SADP approach produces less variation than LELE approach by removing the second pattern misalignment on Si. Although SADP provides better overlay controllability than LELE, it still encounters many challenges. One of the challenges is controlling the 2nd patterning linewidth and uniformity. In general, the Color-B critical dimension (CD) has a larger variation than Color-A CD in the SADP process using Mandrel structure. In this paper, we investigate variations to the SADP Color-B CD based on self-aligned litho-etch litho-etch (SALELE) process flow, including the lithographic CD uniformity, hard mask etching, spacer etch and final Si etch. The corresponding contribution to Color-B CD variation is analyzed each step. After the major contributors to Color-B variation are identified, an experiment was designed to reduce Color-B pattern variation during the process. The silicon results show that compared with the old process condition, the new process can reduce Color-B variation significantly. With this new process, Color-B variation is comparable to Color-A variation.

Background: Overlay (OV) is a very important indicator for characterizing the pattern position accuracy between two layers in an integrated circuit in the manufacturing industry. The self-aligned double-patterning (SADP) process, which is limited to the resolution of deep ultraviolet lithography, is being extensively used for the volume manufacturing of integrated circuits. However, compared to the planar process, the SADP process poses new challenges for OV control.Aim: We investigate the bottom grating asymmetry of a microdiffraction-based overlay (μDBO) target in the SADP process and its effect on OV measurement.Approach: The bottom grating of the OV metrology target is analyzed through scanning electron microscopy and transmission electron microscopy. The imbalance of the −1st- and +1st-order diffraction light intensities of the asymmetrical bottom OV target is characterized. Finally, the effects of light polarization and wavelength on the OV accuracy are simulated.Results: Asymmetric behavior of bottom OV grating is identified. OV dependency on the measurement-light polarization is determined. The simulation results indicate that wavelength and polarization affect the OV accuracy simultaneously.Conclusions: We studied the bottom grating asymmetry-induced inaccuracy in DBO measurement and can assist in understanding the mechanism of measurement light-interaction with the OV grating to enhance the DBO accuracy to a new level.

The integrated circuit (IC) manufacturing factories have measured overlay with conventional "box-in-box" (BiB) or "frame-in-frame" (FiF) structures for many years. Since UMC played as a roll of world class IC foundry service provider, tighter and tighter alignment accuracy specs need to be achieved from generation to generation to meet any kind of customers' requirement, especially according to International Technology Roadmap for Semiconductors (ITRS) 2003 METROLOGY section1. The process noises resulting from dishing, overlay mark damaging by chemical mechanism polishing (CMP), and the variation of film thickness during deposition are factors which can be very problematic in mark alignment. For example, the conventional "box-in-box" overlay marks could be damaged easily by CMP, because the less local pattern density and wide feature width of the box induce either dishing or asymmetric damages for the measurement targets, which will make the overlay measurement varied and difficult. After Advanced Imaging Metrology (AIM) overlay targets was introduced by KLA-Tencor, studies in the past shown AIM was more robust in overlay metrology than conventional FiF or BiB targets. In this study, the applications of AIM overlay marks under different process conditions will be discussed and compared with the conventional overlay targets. To evaluate the overlay mark performance against process variation on 65nm technology node in 300-mm wafer, three critical layers were chosen in this study. These three layers were Poly, Contact, and Cu-Metal. The overlay targets used for performance comparison were BiB and Non-Segmented AIM (NS AIM) marks. We compared the overlay mark performance on two main areas. The first one was total measurement uncertainty (TMU)3 related items that include Tool Induced Shift (TIS) variability, precision, and matching. The other area is the target robustness against process variations. Based on the present study AIM mark demonstrated an equal or better performance in the TMU related items under our process conditions. However, when non-optimized tungsten CMP was introduced in the tungsten contact process, due to the dense grating line structure design, we found that AIM mark was much more robust than BiB overlay target.

The requirement of overlay performance, which is determined by alignment process during exposure and overlay measurement process, is getting tighter as technology node shrinks in integrated circuit. Mark design has drawn a lot of attention since appropriately designed marks can guarantee process compatibility and sufficient device performance tracking property. Cut layers are widely used in FinFet to define active area formed by SADP (Self-aligned double patterning) or SAQP (Self-aligned quadruple patterning), of which the mark design is especially challenging for diffusion break layer since it is a cut layer that landing on three dimensional fin structure and will be aligned to. In this paper, mark design of diffusion break layer is investigated, including alignment marks and overlay marks with various substrates and segmentations. It’s recommended that the whole process from mark definition by lithography to final formation of mark after etch should be well taken into consideration during mark design, along with substrate and segmentation to avoid defect and achieve qualified signal as well.

As the process development is getting tighten, the requirement of process to alignment and overlay Mark gets more and more strict. The accuracy of a Mark measurement plays an important role in semiconductor manufacturing. However, process step in CMP (Chemical Mechanical Planarization), etch and deposition all can contribute to disadvantage impacts and then influence alignment and overlay mark performance. So, how can we determine the accuracy of our measurements? In this study, we focus on different CMP behavior showing a clear expansion map for alignment and overlay mark. By applying default mark under given segment condition, the dishing effect caused by CMP can be significantly improved. At the same time, Mark asymmetry caused by CMP can be significantly reduced by various optimal color weight (OCW) measurements. These behaviors greatly improve the stability of On-Product overlay(OPO), and the rework rate is reduced by 30% on product wafers.

The increasing of wafer size from 200mm to 300mm and downscaling of IC design rule has imposed increasingly tighter overlay tolerances, which becomes very challenging at the 100 nm lithographic node. Such tight tolerances will require very high performance in alignment and overlay measurement. In this paper, we present a concept of total process control of alignment and overlay, which we had used to get deeper understanding of our metal process with W-CMP and aluminum sputter. Traditionally, a lot of works are focusing on alignment process control and overlay process control separately. However, based on what we had observed, the final overlay performance is largely affected by the difference between alignment system (alignment mark, alignment sensor and process) and overlay system (overlay mark, overlay sensor and process). Deeper understanding of this difference between alignment and overlay system do help us to get better overlay process control o and process/tool matching.

In today's semiconductor industry downscaling of the IC design puts a stringent requirement on pattern overlay control. Tighter overlay requirements lead to exceedingly higher rework rates, meaning additional costs to manufacturing. Better alignment control became a target of engineering efforts to decrease rework rate for high-end technologies. Overlay performance is influenced by known parameters such as Shift, Scaling, Rotation, etc, and unknown parameters defined as Induced Variation, which are difficult to control by means of a automation system. In reality, this process-induced variation leads to a strong wafer to wafer, or lot to lot variation, which are not easy to detect in the mass-production environment which uses sampling overlay measurements for only several wafers in a lot. An engineering task of finding and correcting a root cause for Process Induced Variations of overlay performance will be greatly simplified if the unknown parameters could be tracked for each wafer. This paper introduces an alignment performance monitoring method based on analysis of automatically generated files for ASML scanner systems. Because files include alignment results for each aligned wafer, it is possible to use them for monitoring, controlling and correcting the causes of process induced overlay performance without requiring extra measurement time. Since files include alignment information for different alignment marks, it is also possible to select and optimize the best alignment recipe for each alignment strategy. Several case studies provided in our paper will demonstrate how AWE file analysis can be used to assist engineer in interpreting pattern alignment data. Since implementing our alignment data monitoring method, we were able to achieve significant improvement of alignment and overlay performance without additional overlay measurement time. We also noticed that the rework rate coming from alignment went down and stabilized at quite satisfactory level.

Decreasing of node size significantly increases requirement to overlay precision. Complex structure of target demands using of compound structures of overlay mark, which usually contain features with acute sidewall angles, coated by several layers. In this paper the possibility and limitations of image-based overlay with compound structures with overlay mark and coating layers are analyzed in detail. Dependence of overlay signal shape on overlay offset is considered. Structures with asymmetric sidewall angle, non-uniform thicknesses of layers and curved shape of layer borders are examined. Influence of thickness variation, difference between left and right sidewall angles of asymmetric shape and curvature of layer borders are investigated. For the simulation of such complex structures of overlay marks, our in-house simulator based on rigorous coupled-wave analysis (RCWA) module is used. Maximum allowed values of these parameters are studied in order to determine the limitations of image-based overlay. Results of this consideration can be used for improvement of overlay precision and elaboration of optimal overlay strategy in conditions of node shrinking in the semiconductor industry.

It has been demonstrated that the mask-to-mask overlay contribution can be fully characterized by off-line measurements on the PROVE mask registration tool. This characterization includes the impact of the marks that are used for reticle alignment inside the scanner. This is an important aspect since the scanner is blind to the features inside the image field and intra-field adjustments are only based on measurements of the reticle alignment marks. The off-line determined mask-to-mask overlay was compared with the measured on-wafer results and a perfect correlation (R2 < 0.96) was found. The residual mismatch was around 0.6-nm, which is 30% of the dedicated chuck overlay performance of the scanner that was used. These results enable feed-forward corrections to the scanner to improve the intra-field overlay performance or to predict the intra-field overlay originating from mask writing errors (computational overlay). We recently extended the work to the layer-to-layer overlay impact by considering the mask writing error of a wafer alignment mark. This wafer alignment mark was exposed in the first layer. Apart from the reticle writing error of the wafer alignment mark itself, the reticle alignment contribution performed on dedicated reticle alignment marks inside the scanner plays an important role as well. The actual position of the selected wafer alignment mark is also impacted by the reticle alignment model corrections at that specific field location. Only when both contributors are considered, the layer-to-layer overlay can be predicted accurately. In this scenario, the layer-to-layer overlay is measured back to the layer in which the alignment marks were defined. This is referred to as the direct alignment use-case. In this paper, we further investigate the direct alignment use-case in relation to the layer-to-layer overlay. Apart from the reticle writing error and the reticle alignment corrections, the actual placement of the wafer alignment mark during exposure can also be affected by other applied corrections. We will present experimental results of the layer-to-layer overlay as function of the applied automated process corrections on the wafer alignment mark location printed in the first layer. It is shown that the wafer alignment sensor impact should be considered as well in the interpretation of the results. We finally present a strategy to control these kinds of overlay errors.

In leading edge lithography, overlay is usually controlled by feedback based on measurements on overlay targets, which are located between the dies. These measurements are done directly after developing the wafer. However, it is well-known that the measurement on the overlay marks does not always represent the actual device overlay correctly. This can be due to different factors, including mask writing errors, target-to-device differences and non-litho processing effects, for instance by the etch process.1 In order to verify these differences, overlay measurements are regularly done after the final etch process. These post-etch overlay measurements can be performed by using the same overlay targets used in post-litho overlay measurement or other targets. Alternatively, they can be in-device measurements using electron beam measurement tools (for instance CD-SEM). The difference is calculated between the standard post-litho measurement and the post-etch measurement. The calculation result is known as litho-etch overlay bias. This study focuses on the feasibility of post-etch overlay measurement run-to-run (R2R) feedback instead of post-lithography R2R feedback correction. It is known that the post-litho processes have strong non-linear influences on the in-device overlay signature and, hence, on the final overlay budget. A post-etch based R2R correction is able to mitigate such influences.2 This paper addresses several questions and challenges related to post-etch overlay measurement with respect to R2R feedback control. The behavior of the overlay targets in the scribe-line is compared to the overlay behavior of device structures. The influence of different measurement methodologies (optical image-based overlay vs. electron microscope overlay measurement) was evaluated. Scribe-line standard overlay targets will be measured with electron microscope measurement. In addition, the influence of the intra-field location of the targets on device-to-target shifts was evaluated.

As the technology nodes scale down to sub-22 nm, double patterning lithography has been considered as a practical solution for layout manufacturing. Compared with litho-etch-litho-etch, self-aligned double patterning (SADP) has better overlay control. To have a better SADP layout decomposability of routing patterns, we consider SADP during detailed routing stage. Two major types of SADP processes are considered: 1) spacer-is-dielectric type and 2) spacer-is-metal type. Different from previous works, the idea of color preassignment is adopted for SADP-aware detailed routing. An elegant graph model is proposed to capture both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules in detailed routing. We apply a negotiated congestion based rip-up and reroute scheme to achieve better routability while maintaining SADP design rules. Compared with other state-of-the-art academic works, our approach does not produce any side overlay error and no SADP design rules violation is reported. Meanwhile, a better solution in terms of total wirelength, routability, and runtime is achieved.