New alignment mark designs in single patterning and self-aligned double patterning

A more accurate and precise control of overlay performance in lithography process is required as design rule shrinks. Overlay performance is mainly determined by alignment and overlay measurement process, of which alignment and overlay marks play an important role. SADP (Self-aligned double patterning) process becomes widely adopted to realize half pitch of original design for 14nm technology node and beyond. The alignment and overlay marks formed by SADP process differ from traditional ones, which should be well designed to better comply with process condition and reduce the pattern loading effect induced by CMP and ETCH process, and eventually improve overlay performance. In this paper, the alignment behavior of different alignment marks formed via SADP process is investigated. On the other side, the overlay performance of segmented overlay marks is designed and compared with traditional ones to reveal the effect of segmentation on improving the overlay measurement precision and accuracy.

The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer. This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.

Self-aligned double patterning (SADP) is being applied to 7nm technology node and below for back-end metal layers (routing layers) with pitches down to ~40nm. Unlike the traditional litho-etch-litho-etch (LELE) approach, SADP splits pitch using spacers whose 2nd pattern (Color-B) is self-aligned to its 1st pattern (Color-A). As a result, the SADP approach produces less variation than LELE approach by removing the second pattern misalignment on Si. Although SADP provides better overlay controllability than LELE, it still encounters many challenges. One of the challenges is controlling the 2nd patterning linewidth and uniformity. In general, the Color-B critical dimension (CD) has a larger variation than Color-A CD in the SADP process using Mandrel structure. In this paper, we investigate variations to the SADP Color-B CD based on self-aligned litho-etch litho-etch (SALELE) process flow, including the lithographic CD uniformity, hard mask etching, spacer etch and final Si etch. The corresponding contribution to Color-B CD variation is analyzed each step. After the major contributors to Color-B variation are identified, an experiment was designed to reduce Color-B pattern variation during the process. The silicon results show that compared with the old process condition, the new process can reduce Color-B variation significantly. With this new process, Color-B variation is comparable to Color-A variation.

Overlay performance has been a critical factor for advanced semiconductor manufacturing for years. Over time these requirements become more stringent as design rules shrink. Overlay mark design and selection are the first two steps of overlay control, and it is known that different overlay mark designs will have different responses to process conditions. An overlay mark optimized for traditional process might not be suitable for SADP (self-aligned double patterning) technology due to changes in lithography and etching process conditions. For instance, the traditional BIB (box-in-box) target defined by the core mask becomes a template structure in SADP flow, the pitch and cycle of the overlay mark is further changed after spacer formation and core film removal hence the mark recognition and robustness have been challenging for the subsequent process layers. The comprehensive study on the methodology of overlay mark design and selection is still not available for SADP process. In this paper, various types of overlay marks were designed to comply with the SADP process to get rid of the weaknesses of traditional targets. TMU (total measurement uncertainty) performance was adopted to determine the optimal overlay marks for meeting production overlay control requirements in SADP process flow. The results have suggested the segmented marks outperform to non-segmented marks on image contrast as well as TMU.

Background: Overlay (OV) is a very important indicator for characterizing the pattern position accuracy between two layers in an integrated circuit in the manufacturing industry. The self-aligned double-patterning (SADP) process, which is limited to the resolution of deep ultraviolet lithography, is being extensively used for the volume manufacturing of integrated circuits. However, compared to the planar process, the SADP process poses new challenges for OV control.Aim: We investigate the bottom grating asymmetry of a microdiffraction-based overlay (μDBO) target in the SADP process and its effect on OV measurement.Approach: The bottom grating of the OV metrology target is analyzed through scanning electron microscopy and transmission electron microscopy. The imbalance of the −1st- and +1st-order diffraction light intensities of the asymmetrical bottom OV target is characterized. Finally, the effects of light polarization and wavelength on the OV accuracy are simulated.Results: Asymmetric behavior of bottom OV grating is identified. OV dependency on the measurement-light polarization is determined. The simulation results indicate that wavelength and polarization affect the OV accuracy simultaneously.Conclusions: We studied the bottom grating asymmetry-induced inaccuracy in DBO measurement and can assist in understanding the mechanism of measurement light-interaction with the OV grating to enhance the DBO accuracy to a new level.

Design shrinking beyond the resolution limits of 193 nm optical lithography requires the introduction of double patterning technology (DPT) for the semiconductor industry. Two consecutive lithography and etching process (LELE; Litho-Etch-Litho-Etch) and self aligned double patterning (SADP) process are major two options of DPT.In LELE process, layout patterns are decomposed into two groups and each group is placed on a photo mask. The original layout is reconstructed on a wafer through two lithography with two those photo masks. The two lithography processes are independent because of the intermediate process in between, such as etching and resist freeze. Lithography conditions for each mask are optimized on source mask optimization (SMO) technique to enlarge lithography margin. Conventional SMO technique can be applied to the decomposed patterns since two lithography processes have no interaction as discussed above.In SADP process, a layout is also decomposed into two groups as same as the methodology for LELE process. Either decomposed group is transferred on a wafer, which is named as mandrel. Sidewalls are deposited on the mandrel patterns and the following processes such as etching and mandrel removal reconstruct the original layout.Design rules for DPT consist of two parts. One is for an original layout which is drawn by designers. The other is for each decomposed layout printed by a lithography process. Both design rules have interactions because the original layout which follows the former design rules is decomposed into two groups which follow the latter design rules.In this paper, we will discuss the relation between the two rules above. Furthermore, we will discuss the situation on triple or quadruple patterning.

As the technology nodes scale down to sub-22 nm, double patterning lithography has been considered as a practical solution for layout manufacturing. Compared with litho-etch-litho-etch, self-aligned double patterning (SADP) has better overlay control. To have a better SADP layout decomposability of routing patterns, we consider SADP during detailed routing stage. Two major types of SADP processes are considered: 1) spacer-is-dielectric type and 2) spacer-is-metal type. Different from previous works, the idea of color preassignment is adopted for SADP-aware detailed routing. An elegant graph model is proposed to capture both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules in detailed routing. We apply a negotiated congestion based rip-up and reroute scheme to achieve better routability while maintaining SADP design rules. Compared with other state-of-the-art academic works, our approach does not produce any side overlay error and no SADP design rules violation is reported. Meanwhile, a better solution in terms of total wirelength, routability, and runtime is achieved.

Among double patterning techniques, Self-aligned double patterning (SADP) has the advantage of good mask overlay control, which has made SADP a popular double patterning method for sub-32nm technology nodes. However, SADP process places several limitations on design flexibility. This work exploits an alternative post routing approach that has the flexibility to resolve lithography violations without the overhead of repeated rule checking. In addition, it allows for successive refinement in the definition of lithographic violations as the process node matures, and implementation of fixes as localized ECO (Engineering Change Order) operations without needing to reroute the complete design.

It is well known that different alignment mark designs will have different responses to process conditions. An Alignment mark optimized for traditional process might not be suitable for DPS (Double Patterning with Spacer ) technology due to changes in lithography and etching process conditions[1].

Through the continuous scaling with extension of 193-immersion lithography, the multi-patterning process with the grid-based design has become nominal process for fine fabrication to relax tight pitch designs^[1]. In self-aligned type multiple patterning, 7 nm node gate pattern was reported^[2],[3] and it was become a focal point LER on core-pattern is essential category to control pattern placement variations. Though CD uniformity (CDU) on line pattern in self-aligned double patterning (SADP) is relatively stable caused in high thickness controllability of spacer deposition films, the variations of CDU and LER on first core pattern impinge the CDU on space and pitch pattern. In previous study, pattern fidelity of single exposure patterning was improved through photoresist smoothing process using direct-current superposition technique^[4],[5]. In this paper, we will report that photoresist smoothing work in an efficient way to pattern fidelity control in self-aligned type multiple patterning.

Rigorous coupled wave analysis (RCWA) approach is employed to determine electromagnetic (EM) scattering from cylindrical (circular and noncircular) spatially, inhomogeneous, anisotropic material objects. From the late 70's to the present, the RCWA approach has become an extremely important technique for the study of EM diffraction from one and two dimensional planar gratings. RCWA which is a spectral domain technique, is based on expanding Maxwell's equations in a set of Floquet harmonics, and from this expansion, arranging the unknowns of the system in a state variable (SV) form from which a solution may be found. For the study of diffraction from planar gratings, the technique has proved to be a very fast, accurate, and effective method which requires only the solution of relatively small matrix and eigenvalue equations. When the RCWA approach is applied to study scattering from two and three dimensional objects, the theta and phi azimuthal coordinates represent periodic coordinates from which Floquet harmonics may be used to expand the unknowns of the system. Secs. 1 and 2 will review the RCWA method and its application to E-mode planar diffraction gratings. Sec. 3 will present the basic RCWA EM formulation to study scattering from inhomogeneous, anisotopic circular, cylindrical objects, and Sec. 4 will briefly review the RCWA EM formulation used to study scattering from elliptical inhomogeneous objects.

In this paper, we report our research work on developing a Surface Plasmon Resonance (SPR) element with sub-micron (hundreds of nanometers) periodicity grating structure. This grating structure was fabricated by using a simple nano-imprint lithography technique from an organically siloxane polymers, which was then covered by nanometer thin gold layer. The formed grating structure was a very well defined square-shaped periodic structure. The measured reflectance spectra indicate the SPR wave excitation on this grating structure. For comparison, the simulations of reflectance spectra have been also carried out by using Rigorous Coupled-Wave Analysis (RCWA) method. The experimental results are in very good agreement with the simulation results.

Amongst the possible double patterning strategies for sub 32nm processes, self-aligned double patterning (SADP) has moved from Flash-only processes to more general purpose devices. The reason is that while litho-etch- litho-etc (LELE) process was originally preferred due to its simplicity and relative low cost, its sensitivity to overlay error has prompted the search for other methods. Although the basic SADP process is fairly robust against the overlay error, the robustness of 2D SADP method strongly depends on layout and decomposition styles and decomposability compliance. In this paper, we first discuss different printability challenges for SADP method. Afterward, we propose a SADP-aware detailed routing method, by applying a correct-by-construction approach, to provide SADP-friendly layouts. This method performs detailed routing and layout decomposition concurrently to prevent litho-limited layout configurations. Experimental results show that, compared with a SADP-blind detailed router, the proposed method achieves considerable robustness against lithography imperfection in expense of tolerable wire length overhead.

EUV is an ongoing industry challenge to adopt due to its current throughput limitations. The approach to improve throughput has primarily been through a significant focus on source power which has been a continuing challenge for the industry. The subject of this paper is to review and investigate the application of SADP (Self aligned double patterning) as a speed enhancing technique for EUV processing. A process with the potential of running a 16 nm self-aligned final etched pattern in less than 10mJ exposure range is proposed. Many of the current challenges with shot noise and resolution change significantly when SADP is used in conjunction with EUV. In particular, the resolution challenge for a 16nm HP final pattern type image changes to 32nm as an initial pattern requirement for the patterned CD. With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry where the relaxation of both LER and CD together combined, give the resist formulation space a new target when EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final 16nm half pitch target pattern to align with the industry needs. If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added costs associated with the double patterning process. This flow can then be shown to be an enabling approach for many EUV applications.

Decreasing of node size significantly increases requirement to overlay precision. Complex structure of target demands using of compound structures of overlay mark, which usually contain features with acute sidewall angles, coated by several layers. In this paper the possibility and limitations of image-based overlay with compound structures with overlay mark and coating layers are analyzed in detail. Dependence of overlay signal shape on overlay offset is considered. Structures with asymmetric sidewall angle, non-uniform thicknesses of layers and curved shape of layer borders are examined. Influence of thickness variation, difference between left and right sidewall angles of asymmetric shape and curvature of layer borders are investigated. For the simulation of such complex structures of overlay marks, our in-house simulator based on rigorous coupled-wave analysis (RCWA) module is used. Maximum allowed values of these parameters are studied in order to determine the limitations of image-based overlay. Results of this consideration can be used for improvement of overlay precision and elaboration of optimal overlay strategy in conditions of node shrinking in the semiconductor industry.