Characterization and optimization of overlay target design for shallow-trench isolation (STI) process

Background: An overlay target design is essential before performing overlay metrology and has a great impact on overlay performance. In addition, accurate overlay metrology is required to achieve high product yields in semiconductor manufacturing. When asymmetry of the overlay target occurs, it is necessary to increase the area of the pattern existing in the target and stabilize the optical aberration for stable measurement. For this reason, we propose an image-based overlay target design that can secure a larger area compared with the existing overlay target and stabilize the optical aberration by overlapping and exposing the upper and lower patterns of the overlay target.Aim: The effective area of the existing mark design is improved by proposing an overlay target and a measurement method used in image-based overlay measurement.Approach: The proposed overlay target design is configured by arranging different marks orthogonally to the upper and lower layers, and different two-dimensional information can be inserted in the same area. When necessary, single-dimensional information desired by the user can be obtained through a technique called projection, and it has the advantage of using a larger effective area than the existing overlay target.Results: Overlay can be measured using projected signal components, and the possibility and performance of the proposed target can be confirmed through simulation and test wafer. In addition, it was possible to bring about a 15% improvement in total measurement uncertainty performance compared with the existing advanced imaging metrology (AIM) target by taking a wider effective area.Conclusions: An overlay target design is proposed to solve the technical problems of the existing overlay target design. The proposed overlay target has a method that is capable of minimizing the size of the overlay target while maximally maintaining the signal density, a way of reducing the influence of aberration, and various other advantages.In addition, the proposed method provides a design rule that breaks the “lower pattern and upper pattern must not overlap” framework.

In leading edge lithography, overlay is usually controlled by feedback based on measurements on overlay targets, which are located between the dies. These measurements are done directly after developing the wafer. However, it is well-known that the measurement on the overlay marks does not always represent the actual device overlay correctly. This can be due to different factors, including mask writing errors, target-to-device differences and non-litho processing effects, for instance by the etch process.1 In order to verify these differences, overlay measurements are regularly done after the final etch process. These post-etch overlay measurements can be performed by using the same overlay targets used in post-litho overlay measurement or other targets. Alternatively, they can be in-device measurements using electron beam measurement tools (for instance CD-SEM). The difference is calculated between the standard post-litho measurement and the post-etch measurement. The calculation result is known as litho-etch overlay bias. This study focuses on the feasibility of post-etch overlay measurement run-to-run (R2R) feedback instead of post-lithography R2R feedback correction. It is known that the post-litho processes have strong non-linear influences on the in-device overlay signature and, hence, on the final overlay budget. A post-etch based R2R correction is able to mitigate such influences.2 This paper addresses several questions and challenges related to post-etch overlay measurement with respect to R2R feedback control. The behavior of the overlay targets in the scribe-line is compared to the overlay behavior of device structures. The influence of different measurement methodologies (optical image-based overlay vs. electron microscope overlay measurement) was evaluated. Scribe-line standard overlay targets will be measured with electron microscope measurement. In addition, the influence of the intra-field location of the targets on device-to-target shifts was evaluated.

Numerical simulation of overlay metrology targets has become a de-facto standard in advanced technology nodes. While appropriate simulation software is widely available in the industry alongside with metrics that allow selection of the best performing targets, the model validation tools are less developed. We present an approach of numerical model validation based on the comparison between target simulation results and on-product overlay measurements. A “simulation-tomeasurement” software is used in this work to compare the performance metrics and accuracy flags of scatterometrybased overlay targets designed using KLA-Tencor AcuRate™ simulator for the critical layers of 12nm FD-SOI FEOL stack and 22nm FD-SOI BEOL stack. We demonstrate how simulation-to-measurement matching enabled us to verify the model, identify discrepancies between the model and the product stack and build an improved model that correctly describes the target. The refined target stack was used for image-based overlay target simulations that allowed us to obtain better performing optical overlay targets as well.

Metrology target quality highly impacts overlay measurement accuracy and robustness. Factors that can affect target quality include target pattern symmetry, pattern uniformity over one target, and target quality variation within wafer, wafer to wafer and lot to lot. Historically, multiple studies have revealed how metrology pattern asymmetry causes overlay measurement inaccuracy issues. Target design can address pattern asymmetry induced overlay error, to some extent, by providing a process compatible design. Metrology targets synchronously consider process compatibility, metrology system capability and target design basic rule. In some cases, the minimum design rule is constrained by process condition. Staircase loop layers of the 3D-NAND integration process are the typical case where resist thickness limits the accessible minimum CD/pitch. The required larger CD/pitch sometimes even violates the basic design rule of the metrology target. In this study, a novel target design is applied to address thick photo-resist processes. Compared to the baseline, the new target design helps address overlay error induced by pattern asymmetry, thus improving thick resist layers overlay measurement accuracy.

A new shallow trench isolation (STI) process with a mini-spacer at the masking nitride sidewall before silicon trench etching was proposed. With this mini-spacer, thicker corner liner oxide and a T-shaped trench oxide can be formed simultaneously. The issue of oxide-recess at STI corner can be effectively reduced and larger process window for subthreshold kink free device were obtained. The isolation capability and junction integrity were both improved as compared with those of the conventional STI process. Reverse narrow width effect as well as gate oxide integrity were also improved. This technology was employed for 0.13 µm complementary metal oxide silicon (CMOS) device fabrication.

In this paper, in order to obtain layout-independent transistors in recent fine-pitched LSI circuits, a completely stress-controlled shallow trench isolation (STI) process is proposed. In this process, a single-layered spin-on dielectric (SOD) film is used for STI gap filling without employing a complex hybrid structure. With this technique, the mechanical stress caused by STI is markedly suppressed. Subsequently, drain current (Id) modulation due to the STI stress is inhibited successfully. Thus, this technique is a very promising 45 nm node STI scheme with a high performance and a high reliability.

Reduction of oxide leakage currents of EEPROM at STI corners using sacrificial oxide/liner SiN/LPCVD MTO

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 /spl mu/m is achieved with 0.25-/spl mu/m STI. The memory cell is shrunk to 0.29 /spl mu/m/sup 2/, which realizes a 130-mm/sup 2/, 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-/spl mu/s first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 /spl mu/s. That realizes 4.4-Mbyte/s programming throughput.

Overlay control for recording head manufacturing is becoming increasingly challenging as design geometry specifications tighten in the transition to advanced Heated Assisted Magnetic Recording (HAMR) devices. As overlay control requirements for critical patterning layers tighten below 5nm, the need for accurate and robust overlay metrology is key to enabling the patterning roadmap and improving yields. This work focuses on improving Imaged Based Overlay (IBO) metrology to ensure accurate overlay measurements for critical lithography steps in the recording head fabrication process. Selection of the optimal settings for color filter and Numeric Aperture (NA) parameters can have a significant impact on overlay measurement accuracy and Total Measurement Uncertainty (TMU) when setting up a new overlay metrology recipe1-2. These overlay metrology recipe parameters can be selected to minimize the influence of process induced overlay target imperfections on the measured overlay 3. This paper reports our revised workflow for selecting IBO measurement conditions and evaluating pre-existing recipes for robustness. We utilize metrics such as the overlay model residuals, Tool Induced Shift (TIS), and Qmerit error in identifying recipes requiring improvement. The new “Train Log” feature available on KLA’s Archer™ IBO metrology tool platform can be used to compare the through focus contrast precision of different illumination conditions at the time of recipe creation. In this study, we show that an optimization workflow that utilizes the “Train Log” collection of the contrast precision metric and imageless recipes in selecting color filter and numeric aperture settings can significantly improve the overlay measurement repeatability and tool to tool matching.

Overlay performance has been a critical factor for advanced semiconductor manufacturing for years. Over time these requirements become more stringent as design rules shrink. Overlay mark design and selection are the first two steps of overlay control, and it is known that different overlay mark designs will have different responses to process conditions. An overlay mark optimized for traditional process might not be suitable for SADP (self-aligned double patterning) technology due to changes in lithography and etching process conditions. For instance, the traditional BIB (box-in-box) target defined by the core mask becomes a template structure in SADP flow, the pitch and cycle of the overlay mark is further changed after spacer formation and core film removal hence the mark recognition and robustness have been challenging for the subsequent process layers. The comprehensive study on the methodology of overlay mark design and selection is still not available for SADP process. In this paper, various types of overlay marks were designed to comply with the SADP process to get rid of the weaknesses of traditional targets. TMU (total measurement uncertainty) performance was adopted to determine the optimal overlay marks for meeting production overlay control requirements in SADP process flow. The results have suggested the segmented marks outperform to non-segmented marks on image contrast as well as TMU.

Having a well designed overlay metrology target is one of the ways to improve on-product overlay performance. The traditional screening method in which multiple targets types are added to successive reticle tape outs and then evaluated by trial-and-error may not suffice for the 7nm node and beyond. For instance, although segmentation of image-based overlay target has been reported by many as a means for improving overlay measurement, we find that segmentation does not guarantee improvement. In fact it can be undesirable. Fundamental understandings of metrology and wafer process are required to properly design the targets and carefully optimize them for a given process stack involving multilevel measurement. This paper investigates the Blossom, AIM, and scatterometry targets at the FEOL, MOL, and BEOL patterning levels in 7nm node to gain knowledge needed in order to comprehensively map out the overlay target solutions for future nodes.

The with-in wafer non-uniformity (WIWNU) of the material removal rate (MRR) has long been a concern in CMP. For instance, the rapid variation of the material removal rate at the wafer edge, also known as edge effect, requires an exclusion of the wafer edge after CMP. This reduces the yield of the process. In the shallow trench isolation and copper damascene process, the uneven material removal rates across the wafer cause an over-polishing in the regions where the material is removed faster. This causes a degradation of the circuit performance there. The WIWNU will also bring a systematic variation of the circuit performance across the wafer. A better understanding of the mechanisms driving the WIWNU will help to increase the yield and improve the circuit performance.

Overlay control has been one of the most critical issues for manufacturing of leading edge semiconductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay discrepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay (SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns. One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material contrast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface depending on the material properties of underneath structure. SEM-OL measurement using transient voltage contrast has been developed and its capability of overlay measurement has been proven. An overlay measurement algorithm using template matching method has been developed and was applied to dynamic random access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond 3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.

One of future device candidates for the Si platform integration, the Ge pFinFET, is evaluated for two different shallow-trench-isolation (STI) processes at low temperature operation. The effective mobility around 700 cm2/Vs at 77 K is reported for both STI processes, as a result of the compressive strain in the channel. Regarding the OFF-state region, it is found that the substrate current plays an important role at room temperature and for long channels. It decreases up to three orders of magnitude from room temperature down to 200 K, as long as the p-n junction reverse current from the drain to bulk dominates the substrate current.

Front-end-of-line (FEOL) process parameters including virtual substrate (Si/Si/sub 1-x/Ge/sub x/), shallow-trench-isolation (STI) process, and gate oxidation have strong effects on performance and reliability of strained-Si MOSFETs such as gate oxide integrity (GOI), threshold voltage (V/sub TH/ roll-off, reliability behavior including junction breakdown and device isolation characteristics. It is found that gate oxide integrity can be improved by 1 order of magnitude by applying low-temperature, plasma oxidation process as compared with thermal oxidation, junction leakage and device isolation characteristics can be improved by 1 order of magnitude and by two times, respectively, by using low-defect virtual substrate and further defect-curing process, and parameters related with STI process such as thin SiN layer and oxide densification temperature must be optimized both to reduce junction leakage current and to improve device performance such as Ion-Ioff characteristics.