Wafer-Scale Modeling of CMP

The role of non-ionic surfactant concentration in the planarization performance of copper wafer is investigated. The basic components of the slurry contain H2O2, a mixture of benzotriazole (BTA) and ammonium dodecyl sulfate (ADS), FA/O II (macromolecular organic complexing agent), and silica. The static performance of the alkaline slurry including the surface tension, viscosity, particle size distribution and zeta potentials is analyzed. The effect of AEO on material removal rate (MRR) profiles, within-wafer non-uniformity (WIWNU) and surface roughness is also discussed. The AEO in combination with a small amount of BTA and ADS has a large effect on the stability of abrasives, MRR, WIWNU and surface roughness. A new MRR model is proposed to elucidate the polishing mechanism, revealing that the inhibition properties of AEO can be characterized through the corrosion inhibition efficiency and adsorption behavior. An optimal choice of the AEO concentration can achieve a good stability of the slurry, high MRR, low WIWNU and planar surface. The surfactant concentration ranging from 0.1 wt% to 0.5 wt% would contribute to acquiring a good surface planarization performance. Therefore, this work provides a comprehensive understanding of the effect of AEO concentration on the surface planarity of copper CMP in alkaline slurries.

In this paper, in order to obtain layout-independent transistors in recent fine-pitched LSI circuits, a completely stress-controlled shallow trench isolation (STI) process is proposed. In this process, a single-layered spin-on dielectric (SOD) film is used for STI gap filling without employing a complex hybrid structure. With this technique, the mechanical stress caused by STI is markedly suppressed. Subsequently, drain current (Id) modulation due to the STI stress is inhibited successfully. Thus, this technique is a very promising 45 nm node STI scheme with a high performance and a high reliability.

This paper reports a systematic approach for characterizing and optimizing overlay target design to minimize the overlay target noise for shallow trench isolation (STI) process. Sixteen overlay targets were designed and evaluated to determine which target result in the most accurate and reproducible overlay measurements for STI process. The experiment conducted consists of two phase: the first phase is target screening for evaluating sixteen different target designs on STI laser. Each overlay target design is characterized by quantifying the mean TIS, TIS variability, target step height variance, dynamic precision , overlay measurement distribution, kernels signal and modeled residuals. Also, four one-layer inner and outer calibration targets were placed next to the sixteen targets to evaluate the CMP distortion effect on the overlay targets. In the second, phase, short and long-term gauge studies were performed. Stepper offset and correction were tested to verify the accuracy of overlay response. A design of experiment was completed to check robustness of overlay target to process variation in nitride thickness and CMP polishing time with and without the stepper alignment mark clear out process. Overlay measurement accuracy is correlated with SEM cross section to complete the evaluation.

Reduction of oxide leakage currents of EEPROM at STI corners using sacrificial oxide/liner SiN/LPCVD MTO

A new shallow trench isolation (STI) process with a mini-spacer at the masking nitride sidewall before silicon trench etching was proposed. With this mini-spacer, thicker corner liner oxide and a T-shaped trench oxide can be formed simultaneously. The issue of oxide-recess at STI corner can be effectively reduced and larger process window for subthreshold kink free device were obtained. The isolation capability and junction integrity were both improved as compared with those of the conventional STI process. Reverse narrow width effect as well as gate oxide integrity were also improved. This technology was employed for 0.13 µm complementary metal oxide silicon (CMOS) device fabrication.

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 /spl mu/m is achieved with 0.25-/spl mu/m STI. The memory cell is shrunk to 0.29 /spl mu/m/sup 2/, which realizes a 130-mm/sup 2/, 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-/spl mu/s first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 /spl mu/s. That realizes 4.4-Mbyte/s programming throughput.

Chemical mechanical polishing (CMP) is a widely used technique in semiconductor manufacturing to achieve a flat and smooth surface on silicon wafers. A key challenge in CMP is enhancing the material removal rate (MRR) while reducing within-wafer non-uniformity (WIWNU). A computational fluid dynamics (CFD) model is employed to analyze the slurry flow between the wafer and the polishing pad. Several factors influence the CMP process, including the type of abrasives, slurry flow rate, pad patterns, and contact pressure distribution. In this study, two polishing pad patterns with concentric and radial grooves are proposed to address how morphology variations influence wafer removal rate and consistency. Under the same operating conditions, the CFD simulations show that (i) the radial grooves have higher wall shear stress, a more significant negative pressure region, and a more evenly distributed mass on the wafer surface than the concentric grooves, and (ii) the radial grooves exhibit superior slurry mass distribution. It is noted that reducing the negative pressure differential field area results in a less pronounced back-mixing effect. A comparison of radial and concentric polishing pad grooves reveals that radial grooves improve slurry distribution, reduce the slurry saturation time (SST), and increase wall shear stress, leading to higher MRR and improved non-uniformity (NU). Precisely, the errors between the experimental SST values of 21.52 s and 16.06 s for concentric circular and radial groove pads, respectively, and the simulated SST values of 22.23 s and 15.73 s are minimal, at 3.33% and 3.35%.

The within-wafer non-uniformity (WIWNU) of material removal rate in chemical mechanical polishing (CMP) is important for IC manufacture. The non-uniform distributions of polishing pressure and the relative speed between the wafer and the polishing pad are main factors affecting the WIWNU. In this paper，based on the contact mechanics and the elastic plate theory, a compensate pressure computing model is presented, in which the effects of kinematic parameters are taken into acount. By modelling and calculating, the desired compensate back pressure distribution is obtained. In the last section the design of a schematic carrier with multi-zone, in which the compensate back pressure can be applied, is presented. The model and the design can be used for providing theoretical guide to the development of CMP equipments and selection of the kinematic variables in CMP process.

Two radiation hardening processes for shallow trench isolation (STI), i.e., Si+ implantation and STI oxide nitridation are investigated, including the impact on nominal electrical characteristics and radiation hardness. The total ionizing dose effects of the nMOS devices are proved to be sensitive to the STI radiation hardening process conditions. There are optimum process conditions to achieve the best effectiveness of radiation hardening. Then, a 130-nm radiation-hardened PDSOI technology has been developed. The radiation hardness is verified by static random access memories with small storage capacities.

The impact of oxygen in silicon substrates and the formation of oxide precipitates have been widely investigated in the past, because of deleterious electrical recombination and their impact on yield [1]. The presence of oxygen can also be beneficial, with the so-called internal gettering effect by oxygen precipitates. More recently, researchers pointed out the role of interstitial oxygen on the formation of slip lines and dislocations [1-2]. The impact of interstitial oxygen during thermal treatments has to be distinguished from the one of oxygen precipitates for a better understanding of various phenomena [3]. We show in this paper the combined impact of features such as interstitial oxygen, thermal processes and innovating SOI substrates on slip-line generation after complex device fabrication process flows.We have investigated different kinds of silicon and SOI substrates (with silicon obtained with the Czochralski method) that were submitted to different thermal treatments during a specific 65nm process flow targeting Radio-Frequency devices. We have worked on 300mm patterned and blanket wafers and focused notably on a last stressing oxidizing anneal step used for gate oxide formation. One type of SOI substrates had a poly-silicon layer beneath the buried oxide (named SOI Trap-Rich) specifically for RF applications [4]. We have used two kinds of processes, low and high temperature, in Rapid Thermal Oxidation (RTO) tools. Slip-line counts and cumulated lengths were monitored on blanket SOI and Si wafers after main anneal steps and gate oxide RTO, using a Pattern Wafer Geometry (PWG) tool (figure 1). The post-nitridation anneal for gate oxide formation was performed at temperature above 1000°C in single wafer tools. On Si and SOI with 70nm-thick Si layers, no slip-lines were detected using Process-Of-Record conditions (whatever the process temperature). Meanwhile, high temperatures and above all extreme edge offset temperatures (usually used in single wafer reactors to have processes as uniform as possible) resulted in higher slip-line counts and cumulated lengths on the wafers back-sides. On SOI with TR layers, slip-lines were detected whatever the conditions, although they were less numerous with a low temperature and optimized process.Differences for wafers processed at the same time highlighted the influence of several parameters: the thermal history evidenced by wafer-to-wafer variability for SOI wafers with a Trap-rich layer underneath, the stack (SOI type and nature) and the process temperature used during previous oxidation steps. A typical map obtained by the PWG is shown in Figure 2 [5]. Meanwhile, Figure 3 shows a macro Photoluminescence mapping of a blanket Silicon wafer, pointing out the electrical activity of planar defects at the wafer edges (non-radiative recombination on dislocations). A direct relationship was found between the slip-line origin and contact points coming from ring supports at wafers’ back-side (the origins of slip lines). Figure 4 shows the relationship between the oxygen concentration in bulk Si and the silicon handles of SOI substrates, the slip-line counts and wafer warp. Based on this trend, we have also statistically confirmed on patterned wafers processed in a 65nm RF flow, the direct relationship between substrate deformation, low oxygen concentration in the Si handle (lower at wafer edge in agreement with slip line formation) and lithography overlay (OVL) measurements. When OVL exceeded a certain value, residuals (i.e. misalignments due to shifts between patterns which are symbolized by vectors) could not be corrected any more. It is typically what we have on SOI TR substrates with an extreme offset temperature (intentionally too high). An OVL signature out of our range of specifications is shown in Figure 5 on a patterned wafer processed up to gate oxide level. High numbers of slip lines result in OVL over detection. Meanwhile, wafer deformations and more precisely stresses that are too high increase OVL residuals. Above a given threshold, the built-in stress in the wafer is so high that slip lines are nucleated at the wafer edges to minimize the elastic energy. Above a second threshold, the wafer deformation is irreversible. Finally, the relationship between OVL and electrical failure is not straightforward and more often the consequence of mixed parameters such as substrate composition and nature, annealing steps and etching during Shallow Trench Isolation or gate oxide definition.[1] J. Fujise et al, Japanese J. of Applied Physics, 57 (035501) 2018[2] J. Fujise et al, J. Solid State Science and Techn., 9 (055012) 2020[3] G. Kissinger et al, J. Solid State Science and Techn., 8 (N79) 2019[4] B.K. Esfeh et al, Solid State Electronics, 128 (121) 2017[5] V. Brouzet et al, ASMC conference, april 2019 Figure 1

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Random telegraph signal (RTS) noise is of increasing concern for sub-100-nm Flash memories. To quantitatively study the shallow trench isolation (STI) edge effect, NMOS devices with and without STI edges in the channel area are designed and analyzed. The significant impact of STI on width scaling is demonstrated and quantified. It is shown that the noise induced by STI edges dominates the RTS noise for smaller device sizes and is caused by an increase in the number of trapping sites at the STI edges. By rounding the STI corner, the number of stress-induced traps can be significantly reduced. </para>

One of future device candidates for the Si platform integration, the Ge pFinFET, is evaluated for two different shallow-trench-isolation (STI) processes at low temperature operation. The effective mobility around 700 cm2/Vs at 77 K is reported for both STI processes, as a result of the compressive strain in the channel. Regarding the OFF-state region, it is found that the substrate current plays an important role at room temperature and for long channels. It decreases up to three orders of magnitude from room temperature down to 200 K, as long as the p-n junction reverse current from the drain to bulk dominates the substrate current.

The purpose of this investigation is to clarify the origin of the removal rate variation at the wafer edge in Chemical Mechanical Polishing (CMP) by using the floating head with the retaining ring. Within-wafer non-uniformity of removal rate is often determined by the removal rate variation at the wafer edge. Polished edge profile varies with the pressure distribution at the wafer edge. It is strongly affected by the pressure load applied on the retaining ring. Therefore, the non-uniformity of the pressure distribution at the retaining ring could result in the removal rate variation at the wafer edge. It is realized that the flatness of the retaining ring is very important factor for the polished edge profile variation. The same head with the same conditioned retaining ring gives almost the same removal rate variation at the wafer edge, even if the polishing condition is different.

Improvements in device isolation are necessary to meet the demand for increasing transistor layout density for future VLSI technology generations. Efforts to make these improvements are focused primarily on advanced LOCOS and shallow trench isolation (STI) techniques. At Loral, we are currently pursuing STI for our next generation bulk technology. In this work, we adapt the bulk STI process to SOI, and examine some of the issues encountered. STI is integrated with 0.5 /spl mu/m, fully-depleted, accumulation mode devices. N-channel devices are fabricated and device parametrics, reliability, and radiation effects are investigated. The goal for this work was to have functional 0.7 /spl mu/m wide (as-drawn) devices.

The defect density reduction is one of the main challenges to increase the yield. This article presents a mechanism of defect formation specific to the STI module. This defect-flake like - appears during HDP-CVD process deposition. It comes from oxide bubbles localised at the bevel of the substrate. The suppression of this defect consists into the bevel shape optimization. Moreover, process improvement as resist strip post etch contributes to clean the bevel from polymer and reduces strongly the flakes density.