A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology

This paper reports a systematic approach for characterizing and optimizing overlay target design to minimize the overlay target noise for shallow trench isolation (STI) process. Sixteen overlay targets were designed and evaluated to determine which target result in the most accurate and reproducible overlay measurements for STI process. The experiment conducted consists of two phase: the first phase is target screening for evaluating sixteen different target designs on STI laser. Each overlay target design is characterized by quantifying the mean TIS, TIS variability, target step height variance, dynamic precision , overlay measurement distribution, kernels signal and modeled residuals. Also, four one-layer inner and outer calibration targets were placed next to the sixteen targets to evaluate the CMP distortion effect on the overlay targets. In the second, phase, short and long-term gauge studies were performed. Stepper offset and correction were tested to verify the accuracy of overlay response. A design of experiment was completed to check robustness of overlay target to process variation in nitride thickness and CMP polishing time with and without the stepper alignment mark clear out process. Overlay measurement accuracy is correlated with SEM cross section to complete the evaluation.

A new shallow trench isolation (STI) process with a mini-spacer at the masking nitride sidewall before silicon trench etching was proposed. With this mini-spacer, thicker corner liner oxide and a T-shaped trench oxide can be formed simultaneously. The issue of oxide-recess at STI corner can be effectively reduced and larger process window for subthreshold kink free device were obtained. The isolation capability and junction integrity were both improved as compared with those of the conventional STI process. Reverse narrow width effect as well as gate oxide integrity were also improved. This technology was employed for 0.13 µm complementary metal oxide silicon (CMOS) device fabrication.

In this paper, in order to obtain layout-independent transistors in recent fine-pitched LSI circuits, a completely stress-controlled shallow trench isolation (STI) process is proposed. In this process, a single-layered spin-on dielectric (SOD) film is used for STI gap filling without employing a complex hybrid structure. With this technique, the mechanical stress caused by STI is markedly suppressed. Subsequently, drain current (Id) modulation due to the STI stress is inhibited successfully. Thus, this technique is a very promising 45 nm node STI scheme with a high performance and a high reliability.

Reduction of oxide leakage currents of EEPROM at STI corners using sacrificial oxide/liner SiN/LPCVD MTO

The with-in wafer non-uniformity (WIWNU) of the material removal rate (MRR) has long been a concern in CMP. For instance, the rapid variation of the material removal rate at the wafer edge, also known as edge effect, requires an exclusion of the wafer edge after CMP. This reduces the yield of the process. In the shallow trench isolation and copper damascene process, the uneven material removal rates across the wafer cause an over-polishing in the regions where the material is removed faster. This causes a degradation of the circuit performance there. The WIWNU will also bring a systematic variation of the circuit performance across the wafer. A better understanding of the mechanisms driving the WIWNU will help to increase the yield and improve the circuit performance.

Improvements in device isolation are necessary to meet the demand for increasing transistor layout density for future VLSI technology generations. Efforts to make these improvements are focused primarily on advanced LOCOS and shallow trench isolation (STI) techniques. At Loral, we are currently pursuing STI for our next generation bulk technology. In this work, we adapt the bulk STI process to SOI, and examine some of the issues encountered. STI is integrated with 0.5 /spl mu/m, fully-depleted, accumulation mode devices. N-channel devices are fabricated and device parametrics, reliability, and radiation effects are investigated. The goal for this work was to have functional 0.7 /spl mu/m wide (as-drawn) devices.

One of future device candidates for the Si platform integration, the Ge pFinFET, is evaluated for two different shallow-trench-isolation (STI) processes at low temperature operation. The effective mobility around 700 cm2/Vs at 77 K is reported for both STI processes, as a result of the compressive strain in the channel. Regarding the OFF-state region, it is found that the substrate current plays an important role at room temperature and for long channels. It decreases up to three orders of magnitude from room temperature down to 200 K, as long as the p-n junction reverse current from the drain to bulk dominates the substrate current.

Two radiation hardening processes for shallow trench isolation (STI), i.e., Si+ implantation and STI oxide nitridation are investigated, including the impact on nominal electrical characteristics and radiation hardness. The total ionizing dose effects of the nMOS devices are proved to be sensitive to the STI radiation hardening process conditions. There are optimum process conditions to achieve the best effectiveness of radiation hardening. Then, a 130-nm radiation-hardened PDSOI technology has been developed. The radiation hardness is verified by static random access memories with small storage capacities.

Front-end-of-line (FEOL) process parameters including virtual substrate (Si/Si/sub 1-x/Ge/sub x/), shallow-trench-isolation (STI) process, and gate oxidation have strong effects on performance and reliability of strained-Si MOSFETs such as gate oxide integrity (GOI), threshold voltage (V/sub TH/ roll-off, reliability behavior including junction breakdown and device isolation characteristics. It is found that gate oxide integrity can be improved by 1 order of magnitude by applying low-temperature, plasma oxidation process as compared with thermal oxidation, junction leakage and device isolation characteristics can be improved by 1 order of magnitude and by two times, respectively, by using low-defect virtual substrate and further defect-curing process, and parameters related with STI process such as thin SiN layer and oxide densification temperature must be optimized both to reduce junction leakage current and to improve device performance such as Ion-Ioff characteristics.

A simple Shallow Trench Isolation (STI) process is proposed for deep sub-micron DRAM applications. The features of this STI flow are tapered trench sidewalls, a slight trench reoxidation, a vertical B field implant, a CMP-only planarization, and disposable oxide spacers to smooth the trench corners. The scalability of this process makes it suitable for 256 Mb to 4 Gb DRAM generations. >

In this paper, we present a new process flow to increase cell capacitance in planar dynamic random access memory cells designed for system-on-chip applications. Silicon dioxide of shallow trench isolation (STI) under capacitor electrodes is recessed to increase cell capacitance. It appears that the cell capacitance is increased to 25% when the STI recess is 0.15 μm. The recession slightly decreases junction leakage current due to annealing of defects and also relief of STI stress. These combined effects increase refresh time about 50% in 1 Mb memory array. The distribution of breakdown voltage in capacitor oxide shows similar behavior compared with samples without STI recessed. Also, the lifetime of the capacitor oxide evaluated from the Weibull method exceeds 2000 years. © 2004 The Electrochemical Society. All rights reserved.

The defect density reduction is one of the main challenges to increase the yield. This article presents a mechanism of defect formation specific to the STI module. This defect-flake like - appears during HDP-CVD process deposition. It comes from oxide bubbles localised at the bevel of the substrate. The suppression of this defect consists into the bevel shape optimization. Moreover, process improvement as resist strip post etch contributes to clean the bevel from polymer and reduces strongly the flakes density.

Summary form only given. A multiple-Vt high performance, high density and highly manufacturable 0.25 /spl mu/m CMOS technology with a shallow trench isolation process has been successfully developed. Five metal layers with oxide CMP planarization, etchback W plug for borderless contacts/vias, and fully stacked contact/vias were used. Dual gate oxide process (5 nm for 2.5 V core, and 7 nm for 3.3 V I/O or 13 nm for 5 V I/O) with low defect density, and low Vt (/spl sim/0.2 V) or native Vt (/spl sim/0 V) devices for low power and mixed-mode applications are all demonstrated in this technology.

In this paper we study the causes of an unusually high N- channel transistor punch through leakage using a shallow trench isolation process. This resistive short between source and drain exhibits high structural dependence and has a strong dependence on the channel length and the total field edge of the device. Unlike the normal off-channel leakage. The leakage current of this resistive short shows weak dependence on temperature. Such a correlation between leakage and structure is examined for the first time in this paper. Experimentation with various trench liner oxidation schemes and gap-fill densification was the key to resolve the leakage.

The paper presents a multi-layer hardware-in-the-loop (HIL) based testbed for development, evaluation and testing of microgrid operation. The testbed is a configurable setup which can match any microgrid structure. The presented microgrid consists of 15 distributed energy resources (DERs). It includes 4 distributed generators (DGs): a solar plant, diesel generator, 2 constant power sources, 10 distributed loads (DLs): a direct-on-line induction machines, constant power load, 7 passive loads, a three phase rectifier with an active filter and a battery storage system (BSS). Power system and power electronics parts were simulated by a real time simulator. Controllers for the PE converters were real, industrial controllers connected to the real-time simulator. Supervisory control and data acquisition system (SCADA) for the microgrid was designed and connected to the system. The system behavior was analyzed in a number of different scenarios.