3D eWLB (embedded wafer level BGA) technology for 3D-packaging/3D-SiP (Systems-in-Package) applications

Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. There are some restrictions in possible applications for fan-in WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB (embedded Wafer Level BGA) is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. Furthermore, 3D eWLB technology enables 3D IC and 3D SiP packaging with vertical interconnection. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. This paper will highlight some of the recent advancements in 3D eWLB packaging and integration as well as what is being envisioned and developed to address future technology requirements in 3D packaging. The advantage of 3D eWLB technology and applications of 3D packaging will be presented with several examples. The process flow of 3D eWLB fabrication, assembly and packaging challenges, and performance characteristics will be also discussed.

New electronic devices with small size and low power consumption are in demand in recent years. Miniaturization and complex product are required in modern electronics for more functionality in the smaller electronic package. To overcome such issues, 3D packages or package on package (PoP) are introduced. The 3D packaging is stacking of chip on top of another which is emerging as a powerful technology that satisfies such integrated circuit (IC) package demands. A 3D package using through silicon vias (TSVs) has emerged as an effective technology for future interconnection requirements. The mismatch of coefficient of thermal expansion (CTE) of the SiO2 and copper used in TSV can induce a lot of thermal stresses. The stress developed at interfaces results in the interfacial delamination of TSV, which is mainly driven by a shear stress concentration at the point. The developed thermal stresses are critical for the thermo-mechanical reliability of the 3D package. In this paper, the effect of package structure on the failure metric of the 3D package has been studied. J-integral has been used to quantify the crack driving force. The crack is modeled at the TSV and BEOL (Back End of the Line) and the die-substrate thickness is varied and studied during chip attachment process and under thermal cycling load for optimizing the die and substrate thickness design [1]. Finite Element method have been used to analyze the thermo-mechanical stresses and fracture parameters in TSV structures 3D package. For this study, full field compact modeling methodology [2] has been leveraged for the ease of FEA using ANSYS Workbench 17.2. An optimized package assembly was obtained to reduce the crack driving energy at the TSV region and in the BEOL dielectric layer. A design approach has been proposed to mitigate brittle failure issues thus improving the thermo-mechanical reliability of the 3D package.

Increasing demand for new and more advanced electronic products, with smaller form factor and superior functionality and performance, while reducing the cost, has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies. 3D packaging, using z-axis through silicon via (TSV) stacking concept has been and continues to be investigated by many of the semiconductor manufacturers and research institutes and is believed to be one of the most promising, if not the most promising concept that could successfully address the limitations of today's packaging technologies. There is a continuous increase of interest in development and study of applicability of this new chip stacking approach to existing and future devices; currently, more than fifty companies worldwide are involved in some sort of 3D TSV packaging developments. There are several steps involved in 3D chip stacking using TSV technology. Each of these steps requires different techniques, materials and processes, applications that have to be well understood and integrated in order to successfully be applied. This paper will address various electrodeposition processes applied to form 3D interconnects, from TSV deposition, which is the main metallization step that stays at the hearth of this new technology, to other metallization steps for additional connections, such as bumping and redistribution layers, already well known and applied processes in current wafer level packaging (WLP) applications. Advantages and difficulties associated with each of these technologies, with more focus on 3D vertical integration using TSV copper interconnect, including the approaches taken to overcome them, will be presented. Deposition conditions for bumping were optimized in order to enable higher deposition rates. For other through- mask applications, such as redistribution lines (RDL), the complexity of the pattern, deposition rate, chemical formulation and process parameters were found to have a significant effect on within-die (WID) thickness distribution. In case of WLP structures of thick metal and high aspect ratios, seed layer uniformity proved to be essential for achieving void-free deposition. Void-free structures, especially for high aspect ratio vias seeded with dry methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), seem difficult to obtain. New approaches, such as seed layer repair (SLE) or direct on barrier electrodeposition (DOB) can provide superior uniformity and coverage of the conductive layer, necessary for a uniform nucleation of copper electrodeposition process along the entire sidewall of the via, at significantly lower costs. This paper will present TSV structures obtained with wet chemical processes applications for both seed layer and via filling. Besides seed layer uniformity, additional factors were identified to also be critical for successfully filling deep vias. They are: via profile, wettability of vias, superior performance of chemistries and high performance equipment. By selecting the most appropriate deposition methods and optimizing the chemical formulations together with the process parameters, void-free TSV structures can be obtained.

As the MEMS (Micro-Electro-Mechanical Systems) devices head towards smaller form factor and greater functionalities, improvement in WLCSP (Wafer Level Chip Scale Package) technology is necessary to meet the new requirements from today's electronic devices. TSV (Through Silicon Via) technology has always been used as the vertical interconnections for assembly of MEMS-WLCSP packaging. In our development work, we proposed to use an innovative approach to substitute the TSV with TMV (Through Mold Via), using the wafer-level over-molding of vertical Si (silicon) pillars and Cu (copper) wires as vertical interconnections. For the molding process development work, epoxy mold compound (EMC) and silicone mold compound (SMC) materials were studied to explore suitable mold material candidates for good wafer warpage control and void free vertical interconnects structure mold filling. Fine filler (EMC) B and (EMC) C molded to a thin over-mold cap of 150μm gave void free mold fill and the best wafer warpage control for subsequent Cu (cooper) redistributed layers (RDL)s processing. Liquid (EMC) B was observed to be more suitable for encapsulating vertical wires than granular (EMC) C as random wires collapse was observed after the molding process. Greater Cu smearing on the exposed Cu wire interconnections was observed on (EMC) C as compared to (EMC) B after the mold cap was back-grinded to expose the vertical interconnects. Greater Cu smearing could be attributed to the lower modulus for (EMC) C, which resulted in greater galling after back-grinding and greater Cu smearing. In conclusion, the (SMC) candidates have good wafer warpage control, but were not suitable for our MEMS-WLCSP process flow due to void presence in (SMC) D and flattening of wires for (SMC) E. Hence, (EMC) B and (EMC) C were shortlisted for actual wafers molding development.

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (<2.5mm), low pin counts (<25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is subject to the price-pressure that accompanies this transition. More recently, the semiconductor industry has seen advances in WLCSP technology which have enabled the qualification envelope to be expanded to products with pin counts > 120. These advances have facilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory, many of which require advanced silicon technology nodes as well. Consequently, WLCSP is expanding to markets and applications previously supported by QFN and flip chip CSP. This expansion puts additional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is further enhanced by the changing business models and supply chain strategies adopted by companies in the new economic environment. To meet these growing market demands, WLCSP providers are faced with the challenges of providing faster cycle times and higher capacity without significant increases in capital expenditure. The above factors have driven the need for new WLCSP technologies that utilize fewer process steps compared to common WLCSP product offerings, while maintaining the robustness necessary for meeting quality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to cater to the cost and performance requirements of the diverse application space. This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows. This paper will examine material options, i.e., polymers and solder alloys, for these new structures and will also examine the effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modes produced during reliability testing will be coupled with mechanical simulations to enhance understanding of the failure mechanisms and to further strategies for improving product reliability.

Packaging technologies such as fan out wafer level packaging (FOWLP) and embedded chip in substrate technologies have gained a lot of attention recently from OEMs, OSATS, technology developers, and technology integrators in the integrated circuit (IC) industry as schemes for continuing wafer level chip scale package (WLCSP). Both technologies are focused on incorporating ICs into their packaging platform and on taking advantage of current process recipes and infrastructure as much as possible. However, by virtue of the new process steps and technologies required to get to 3-D packaged materials, such as through silicon vias (TSVs), wafer thinning and handling processes and requirements for alternative dielectric materials, many opportunities have arisen. Expectations are that many devices that follow a flip chip ball grid array (FCBGA) flow or WLCSP will adopt an embedded technology strategy for future generations. FOWLP has several advantages, over FCBGA and WLCSP including potential for system in package (SIP) configurations and 3-D integration, the ability to overcome pad limitation issues, and shorter interconnections and so higher electrical performance. However, to gain these advantages, requirements for processing will change due to the significant demands imposed on the materials used as permanent dielectric layers and the photoresists used in the fabrication processes. Cleaning chemistry must be designed to remove challenging films such as photoresists and residues created during other process steps; yet preserve the exposed metals such as the bond pads and Cu redistribution lines, as well as the permanent dielectrics. Device reliability and performance is heavily dependent on the proper working of all these components. The focus of this paper is to identify a manufacturable and reliable process and process window for removal of positive photoresists and residues in formation of under bump metallization (UBM) and contact pads in wafer level packaging (WLP). Our objective is to discuss a proven process that has been successfully implemented into a manufacturing environment. It has improved robustness and reliability over past-used solutions due to decreased sensitivity to moisture contamination, a significant cause of defects in many device applications.

In recent years, semiconductor chips have been shrunk down drastically in order to achieve higher signal propagation, lower power consumption, lower fabrication cost, and reduced form factor, among others. As semiconductor industry struggled to keep up with adding more functionality into smaller and smaller geometries, Moore’s law has finally reached its limitation without new ground-breaking technologies in processing and assembly. Vertical integration, i.e., 3DIC or 3D packaging, has emerged as the most promising technology to achieve the above goals.Silicon interposer, using through silicon via (TSV) becomes a key part of this 3DIC technology evolution. Traditional TSV fabrication involves deep reactive ion etching of silicon via, chemical vapor deposition (CVD) or physical vapor deposition (PVD) of barrier and seed layers inside the via, and electrochemical deposition (ECD) of copper to fill the via. [1]ECD chemistry is arguably the most important factor to deliver a void free, cost effective bottom-up fill with low overburden in the TSV fabrication. Due to the reasons of long process time, tight process windows, and consumption of organic additives in the ECD process, an accurate chemical analysis of the plating bath is essential to control the ECD process, quality and uniformity in via fill.This paper discusses using cyclic stripping voltammetry (CVS) and cyclic pulse stripping voltammetry (CPVS) to control a TSV via fill chemistry. The process window of this chemistry is so tight that a slight imbalance of the additive would result in via fill from a complete bottom up fill to a complete conformal fill, so an accurate correlation of the CVS responses is needed.Fig. 1 is a typical voltammogram in copper virgin makeup solution. Voltage sweep starts at region 1 and goes to region 2 for electrode surface clean. Region 3 is for the organic absorption on electrode surface. Region 4 is for copper deposition. Region 5 is the copper stripping peak.Organic additive such as suppressor will absorb on the electrode surface to minimize copper plating, as shown in Fig. 2. Copper stripping peak current decreases as the suppressor concentration in the solution increases. Accelerator, on the other hand, will compete with suppressor absorption on the electrode surface to cause an increase in the copper stripping peak current.Accelerator analysis is typically done with response curve (RC) method. A response curve is generated by plotting the Ar/Ar0 ratio a range of accelerator concentrations that cover the accelerator concentration in the actual plating bath. Ar is the stripping peak area with addition of accelerator. Ar0 is the stripping peak area in VMS. Plating bath samples are analyzed in the same way by plotting the Ar/Ar0 ratio and finding the corresponding accelerator concentration, as shown in Fig. 3.To cover a wide of accelerator concentrations in the analysis, different standard solutions must be prepared and analyzed. The CVS response is corrected based on the linear regression model from the results of the standard solutions. The corrected values are then plotted against the CVS responses for precision check to ensure that this CVS analysis method can be used to analyze plating bath samples with a wide range of accelerator concentration.In the tertiary organic system the organic additives compete with each other for absorption sites on the electrode surface. The presence of suppressor and leveler will impact the accuracy and precision of the accelerator analysis. The impact of leveler on accelerator analysis is shown in the Fig. 4. In order to get an accurate accelerator analysis, the concentration of leveler must be high enough such that the electrode surface is fully suppressed before addition of accelerator.Accurate and precise chemistry control is essential for manufacturable TSV fill. This paper outlines the methodology for achieving this control.[1] C. Uzoh, et. al., “Deposition Process for Competitive Through Silicon Via Interposer for 3D”, 8th Annual International Wafer-Level Packaging Conference (2012).

With reducing of silicon techno, the pitches and pads at the chip to package interface become important factor. This drives interconnection toward to fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. Fan-out WLP has the potential to realize any number of interconnects at any shrink stage of the wafer node technology.

The technique of the through silicon via (TSV) filling with copper plays an important role in the 3D packaging to miniaturize connection distance, decrease energy consumption and improve integration density. The nano-scale TSV of the vertical interconnection is obligatory to be developed to reach sub-micron interconnect pitches. However, the reliability of the nano-TSV is a serious concern because thermo-mechanical stresses are varied in the TSV under thermal loadings due to the mismatch of the coefficients of thermal expansion (CTE) between the copper and the surrounding silicon. The high stresses may cause crack propagation and even failures. In this study, the finite element analyses (FEA) for the nano-TSV array with different sizes and patterns were performed. The submodeling method was used in the analysis for a 3D packaged device to reveal the influence of the critical parameters, i.e., the aspect ratio of TSV, the ratio of pitch to diameter and the TSV array layouts. The trilateral and quadrilateral layouts of nano-TSV array were considered in the analysis. Thus, appropriate design suggestions for the nano-TSV array were proposed. The study results assist to optimize the nano-TSV geometry and improve the reliability of the 3D package with nano-TSV.

Wafer level encapsulation is an important packaging process for several components in mobile and high-performance computing applications. In mobile applications, electronic components like application processors, radio-frequency System in Package (RF-SiP) and antenna modules are being manufactured using wafer level fan-out processes. In HPC, wafer level encapsulation is used for chip-on-wafer (CoW) processing and 2.5D / 3D packaging that enables wafer level packaging of processors and high band width memory devices. Although encapsulant materials are currently used in mass production, many pain points remain unresolved. These are predominantly related to lowering the wafer level warpage to enable better handling of wafers during processing, addressing the environmental and EU REACH regulatory compliance, providing better total cost of ownership to the end user by improving throughput and various other factors. In our development, we aim to address these pains and we will present our progress in this research paper. As the structural material in the package, molding compound can cause severe warpage issue during process, becoming the limiting factor to pursue thinner packaging design and causing serious wafer handling issues in the equipment during wafer processing. However, we considered a new material design route to develop ultra-low warpage LCM materials that can dramatically reduce the warpage thereby benefitting various WLP packaging design, such as Fan-in or Fan-out type. We have successfully demonstrated more than 70% improvement in warpage compared to traditional LCM compound. This new type of LCM material is REACH compliant and shows good warpage stability after high temperature annealing process. The polymer relaxation study shows the unique relaxation behavior leading to the warpage stability that is critical in many Fan-out processes. Dynamic Mechanical Analysis is the useful tool to study the relaxation behavior that can differentiate the impact of various chemistry on epoxy molding materials. Another key advantage of our LCM is the excellent gapfilling capability that can lead to the protection of high density structures in semiconductor packages with finer die-to-die or die-to-substrate spacing, meanwhile enabling low-warpage and simpler processing steps. Moreover, the new LCM design can help further shorten the molding time, allowing for increased throughput resulting in lower cost of ownership for the end users.

This paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

Simulation and fabrication of two Cu TSV electroplating methods for wafer-level 3D integrated circuits packaging

In this paper we present a novel low-cost wafer level packaging technology for surface acoustic wave (SAW) filter devices which provides quasi-hermetic device sealing and full compatibility to surface mount assembly technology. The wafer level packaging concept is based on sealing each sensitive SAW structure with a LiTaO3 cap while keeping the peripheral IO pads of the devices accessible. To enable such a process scheme LiTaO3 posts with adhesive bonding frames were pre-processed from LiTaO3 wafers and subsequently bonded to the SAW device wafers using thermo-compression type wafer-to-wafer bonding processes. Subsequently, the wafers with the pre-processed post structures were back-ground to separate the bonded cap structures on the device wafers. A subsequent balling of the peripheral pads with pre-formed SAC305 solder balls finalized the wafer level processing. The process was developed using 403 MHz SAW devices for MICS (Medical Implant Communication Service) band application. Process flow for fabrication and assembly of the SAW filter CSPs with final dimensions of 1.7 × 1.5 × 0.45 mm3 as well as the measured electrical performance will be discussed in the paper. Additionally, options for process modifications regarding size and cost reduction will be presented.

Thermal conduction and mechanical stresses in through silicon via (TSV) structures in three dimensional system in package (3D SiP) under device operation condition were discussed. A large scale simulator, ADVENTURECluster® based on finite element method (FEM) was used to simulate the effects of voids formed inside Cu TSVs on the thermal conduction and mechanical stresses in the TSV structure. The thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses in the TSV structure in 3D SiP were carried out under thermal condition due to power ON/OFF of device. In case that void was not present inside the TSV, the stresses in TSV were close to the hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. Maximum principal stress of the Si chip in the TSV structure for the case without voids was lower than that of the bending strength of silicon. However, the level of the stresses in the Si chips should not be negligible for damages to Si chips. In case that void was present inside the TSV, stress concentration was occurred around the void in the TSV. The magnitude of the equivalent stress in the TSV was lower than the yield stress of copper. The magnitude of the maximum principal stress of the Si chip was lower than that of the bending strength of silicon. However, its level should not be negligible for damages to TSVs and Si chips. The stress on inner surfaces of Si chip was slightly reduced due to the presence of a void in the TSV.

Chip stacking has emerged as the best solution to reduce the packaging size (Karnezos, 2004). Several approaches are proposed by companies and laboratories and each of them presents specific advantages and drawbacks (Tummala, 2004). Today, major 3D applications are stacked memory DRAM, SRAM or flash. Moreover, cost acts as a brake on 3D expansion in SiP and further developments are necessary to reduce the packaging cost. One clearly identified way is to perform collective processes. New developments on wafer level packaging and 3D packaging are lead in a European project (called Walpack) (Poupon, 2004; Souriau, 2005) to fulfil the requirement of the company 3D-PLUS. The proposed technology aims to realise 3D modules, as 3D-PLUS already produces, but using ultra thin components inside. To realise such module, the original approach consist in reconstituting a wafer with the active sides aligned in the same plane, embedded in a resin which gives the wafer its mechanical consistency. The known good re-built chips are then stacked and 3D interconnected by means of the patented 3D-PLUS process