Failure Analysis and Process Improvement for Through Silicon Via Interconnects

Hybrid Wafer-Level Packaging for RF-MEMS and Optoelectronic Applications

In this paper we present the process and electrical results of a 3D integration using through silicon vias (TSV). A flash memory chip has been directly connected to a processor die. The TSVs have been applied from the wafer front-side into a fully processed advanced CMOS 300 mm wafers using a via last approach. After dry etching the 20 by 107 μm holes into the substrate an isolation and barrier seed films are deposited and then filled with copper. The electrical connection between the pad level of the processor chips and the interface to the external connections is realized with a two level redistribution wiring. Subsequently the wafer is flipped, temporary bonded to a carrier wafer, thinned and the TSVs are connected from the wafer backside. Finally the flash chips are assembled to the controller die using a die-to-wafer (D2W) technique. Electrical tests have been conducted and a high yield after TSV processing and assembly determined. The isolation properties and electrical resistance was measured. The linear current in stress transistors was used to define a keep out zone.

Through silicon vias (TSVs) provide advanced vertical interconnections solutions for system-in-package (SiP) (such as chip to chip, chip to wafer, and wafer to wafer stacking), wafer-level packaging, interposer packaging. At present the shortest electrical path (vertical electrical feed through) between two sides of a silicon chip is one of the important applications. In order to achieve high density and high performance package, TSVs technology has been developed. And for three-dimensional (3D) MEMS (Microelectromechanical System) packaging, TSVs are the most important enabling technology. In this paper, some advantages of TSVs technology are described, and process flow of TSVs module is introduced firstly. Subsequently, a novel electricity test method of Non-Ideal Planes for TSVs is introduced. Finally, many critical issues and challenges of TSVs are reviewed.

Via last TSV (through silicon via) technology is more and more applied in 3D WLCSP, which can decrease package volume and increase I/O density. The process of via last includes temporary bonding, grinding, photolithograph, silicon etching, SiO 2 etching, CVD, PVD, plating and so on. Silicon etching and SiO 2 etching are important process of via last TSV package for interconnect technology. Temporary bonding and grinding will affect TTV of silicon wafer, which can cause “notch” and “footing” in etching process. This paper presents a typical process of via last TSV package. The front pillar will choose Cu/Ni/Au, and thickness is 10um/3um/0.05um for flip chip package with other dies. The backside pillar can be Cu/Ni/SnAg. The thickness of silicon wafer will attain 100um, and CD of via can be 35um. The result of O/S test can be 99%. The reaction time ratio of SF 6 and C 4 F 8 is 2.5∶1. The etching flow of SF 6 is 300sccm, and the passivation flow C 4 F 8 of is 180sccm. The scallop can be about 50nm. Higher bias ratio frequency can increase CD of via. 10% duty cycle can improve notch phenomenon. A metrology for thickness of SiO 2 at the bottom of vertical via is used online, which can help to decrease open risk of SiO 2 residual.

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO 2 , the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO 2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO 2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.

In this paper a low temperature ‘via-last’ technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the design of the TSV will be presented and a first approach of a design rule definition for TSV will be introduced. The alignment strategy will be also presented, and specific patterns to succeed front side to back side alignment will be described. In a second part the steps of the Through Silicon Vias (TSV) technology will be presented: glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like double side lithography, silicon deep etching, silicon side wall insulation, vias metallization and final bumping. A special focus will be done on this paper on the TSV metallization step and especially on the chemical seed layer etching. A study has been achieved in this project in order to optimize this part of the process and the results will be shown. Then, morphological and electrical characterizations of the via-last technology will be presented and discussed. Finally, a picture obtained with the TSV CMOS Image Sensor (TSV CIS) will be shown.

In this paper, we design a new program to achieve carbon nanotubes through silicon vias (TSV) interconnects compatible with CMOS technology using an auxiliary TSV structures and laser local heating method. Auxiliary TSV structures are made by two wafers. One wafer is etched into ups and downs structures and then deposited SiN x and SiO 2 film. The other one is made into TSV structures by deep silicon etching, depositing thin film and wafer thinning and polish. Two wafers are bonded together by patterned BCB (Benzocyclobutene). For the entire device structures, we use FDTD solutions software to simulate infrared optical properties of SiN x . SiN x film layer can absorb 10.6 µm infrared laser strongly. Thermal simulation of geometrical model by COMSOL Multiphysics software shows well temperature compatibility. It turns out the program is compatible with current CMOS processes. Using a laser local heating method, we have studied the local growth of carbon nanotubes. Carbon nanotubes grown in TSVs are sparse, intertwined and have a poor morphology; the reason for this is that TSVs' geometric sizes limit gases flows. Carbon nanotubes interconnect still need further study.

Through Silicon Via (TSV) can be used to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1-3]</sup> . Via Reveal-a kind of wafer back side process moduleplays an important role in the successful implementation of TSV. In via-first and via-mid TSV integration flows, Si must be removed from the backside of the wafer to make contact with the bottom of the TSVs. This operation is performed using a mechanical grind followed by a reveal etching process. So in this paper, we will focus on the TSV reveal unit process. Firstly, we will briefly review TSV integration technology; Then a set of experiments is described which were used to select etch parameters to achieve the desired etching rate, selectivity and profile. Lastly we will show the results of TSV reveal using wet etching process. The proper composition of the HNO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HF/CH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> COOH(HNA) solutions, etching parameter, and TEOS deposited by proper temperature provide the necessary process control and etching selectivity that enable the use of higher throughput wet etch for TSV back etch.

The alignment and overlay performance of an ASML PAS5000 waferstepper is reviewed in relation to 3D integration and wafer level packaging (WLP) processes. The alignment system can be used to measure substrate distortions in wafer bonding and waferthinning processes and it can align with high accuracy through thick films. Moreover, it is demonstrated that in through silicon vias (TSV) processing the front- to backwafer overlay accuracy is limited by the etch process, not by the alignment system. An accurate fully functional alignment system can therefore be used to characterize and improve the overlay in 3D integration and WLP processes.

In recent years, semiconductor chips have been shrunk down drastically in order to achieve higher signal propagation, lower power consumption, lower fabrication cost, and reduced form factor, among others. As semiconductor industry struggled to keep up with adding more functionality into smaller and smaller geometries, Moore’s law has finally reached its limitation without new ground-breaking technologies in processing and assembly. Vertical integration, i.e., 3DIC or 3D packaging, has emerged as the most promising technology to achieve the above goals.Silicon interposer, using through silicon via (TSV) becomes a key part of this 3DIC technology evolution. Traditional TSV fabrication involves deep reactive ion etching of silicon via, chemical vapor deposition (CVD) or physical vapor deposition (PVD) of barrier and seed layers inside the via, and electrochemical deposition (ECD) of copper to fill the via. [1]ECD chemistry is arguably the most important factor to deliver a void free, cost effective bottom-up fill with low overburden in the TSV fabrication. Due to the reasons of long process time, tight process windows, and consumption of organic additives in the ECD process, an accurate chemical analysis of the plating bath is essential to control the ECD process, quality and uniformity in via fill.This paper discusses using cyclic stripping voltammetry (CVS) and cyclic pulse stripping voltammetry (CPVS) to control a TSV via fill chemistry. The process window of this chemistry is so tight that a slight imbalance of the additive would result in via fill from a complete bottom up fill to a complete conformal fill, so an accurate correlation of the CVS responses is needed.Fig. 1 is a typical voltammogram in copper virgin makeup solution. Voltage sweep starts at region 1 and goes to region 2 for electrode surface clean. Region 3 is for the organic absorption on electrode surface. Region 4 is for copper deposition. Region 5 is the copper stripping peak.Organic additive such as suppressor will absorb on the electrode surface to minimize copper plating, as shown in Fig. 2. Copper stripping peak current decreases as the suppressor concentration in the solution increases. Accelerator, on the other hand, will compete with suppressor absorption on the electrode surface to cause an increase in the copper stripping peak current.Accelerator analysis is typically done with response curve (RC) method. A response curve is generated by plotting the Ar/Ar0 ratio a range of accelerator concentrations that cover the accelerator concentration in the actual plating bath. Ar is the stripping peak area with addition of accelerator. Ar0 is the stripping peak area in VMS. Plating bath samples are analyzed in the same way by plotting the Ar/Ar0 ratio and finding the corresponding accelerator concentration, as shown in Fig. 3.To cover a wide of accelerator concentrations in the analysis, different standard solutions must be prepared and analyzed. The CVS response is corrected based on the linear regression model from the results of the standard solutions. The corrected values are then plotted against the CVS responses for precision check to ensure that this CVS analysis method can be used to analyze plating bath samples with a wide range of accelerator concentration.In the tertiary organic system the organic additives compete with each other for absorption sites on the electrode surface. The presence of suppressor and leveler will impact the accuracy and precision of the accelerator analysis. The impact of leveler on accelerator analysis is shown in the Fig. 4. In order to get an accurate accelerator analysis, the concentration of leveler must be high enough such that the electrode surface is fully suppressed before addition of accelerator.Accurate and precise chemistry control is essential for manufacturable TSV fill. This paper outlines the methodology for achieving this control.[1] C. Uzoh, et. al., “Deposition Process for Competitive Through Silicon Via Interposer for 3D”, 8th Annual International Wafer-Level Packaging Conference (2012).

Void growth in through silicon vias (TSVs) has been imaged by X-ray microscope without physical cross sectioning. In additional, a finite element stress modeling is used to study the stress-assisted void growth. Fabrication of through silicon vias (TSVs) is challenging and often hampered by the presence of seam-line or voids inside the TSVs as pre-existing void. Annealing these TSVs induces large hydrostatic stress gradient distribute around the pre-existing void. This hydrostatic stress gradient is the driving forces for the vacancies to diffuse to the pre-existing void region and causing void growth. Because physical cross sectioning of TSVs is not required for the 8KeV lab-based X-ray microscope, the same TSVs can be imaged before and after annealing. Void growth is observed at the pre-existing void location after annealing in TSVs with 5μm in diameter and 26 μm of depth. Stresses in a copper-filled TSV with a pre-existing void were simulated by finite element methods and will be presented. The maximum of hydrostatic stress gradient is found to be around the void when cool down from annealing temperature to room temperature. The comparison between simulated results and experimental data show that void growth in TSV is stress-assisted, where vacancies diffuse and coalesce at the void as a result of the hydrostatic stress gradient.

In this paper, we show the advantages of 3-D stacked through silicon via (TSV) in high chip density package in aspect of wideband and low power distribution network (PDN) impedance. We selected large size (80 μm) and large pitch (200 μm) TSV with thick silicon substrate (Si, 80 μm, aspect ratio =1) for on-chip PDN, and compared two total PDN impedances of a PDN with TSVs and a PDN with wire-bondings depending on number of stacked chips from 2 to 10 on a single package. PDN impedance with TSVs includes total capacitance and inductance of TSV and 20 mm × 20 mm package substrate. PDN impedance with wire-bondings shows total capacitance and inductance of wire-bondings and same size package substrate. PDN impedance with TSVs has lower levels with wide bandwidth from 10 MHz to 5 GHz except serial resonance frequency range of the package substrate around 350 MHz. In low frequency range from 10 MHz to 350 MHz, total capacitance of a PDN with TSVs is larger than that of a PDN with wire-bonding because of 0.1 μm thickness silicon oxide (Si02) for blocking DC leakage from TSV to Si substrate. Over 350 MHz, total inductance of a PDN with TSVs is smaller than that of a PDN with wire-bonding because TSV is the smallest electrical path from top surface of stacked chips to the package PDN. The effectiveness of lowering total PDN impedance is better when the number of stacked chips is growing because total length of TSVs is linearly increased with factor 1 while total length of wire-bonding is done with factor √2.

Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops.

To confirm the effectiveness of the via-last through silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer, we evaluated the metal contamination caused by this process. The metal contamination generated near the TSV was investigated by measuring the reverse-bias leakage current of n+/p diodes placed near the TSV. The TSV diameter was 6 µm and the n+/p diode size was 0.6 × 2 µm. The distance between the n+/p diodes and the TSV was 1-10 µm. The notching size was controlled by the etching time. The reverse bias leakage current was small regardless of the distance between the TSV and n+/p diode when the notching size was small (

A double-sided and ultrathin 3-D glass interposer with through package vias (TPVs) at same pitch as through silicon vias (TSVs) in silicon interposers is developed to provide a compelling alternative to 3-D IC stacking of logic and memory devices with TSVs. The 3-D IC stacking approach to achieve high bandwidth has several drawbacks, including the need for TSVs through the logic die, thermal management within the 3-D stack, and the high manufacturing cost associated with wafer-based TSV processing. This paper presents design, fabrication, and electrical characterization of small TPVs (15–40 $\mu{\rm m}$ in diameter) in 30- $\mu{\rm m}$ thin glass to achieve an ultrathin 3-D interposer. This paper also reports the first demonstration of ultrasmall TPVs in glass (15 $\mu{\rm m}$ ) with same dimensions as TSVs in silicon. The signal insertion loss and crosstalk behavior of TPVs in ultrathin glass were investigated and found to be superior to TSVs using 3-D electromagnetic simulations. In demonstrating the 3-D interposers, two process-related challenges were addressed in this paper, namely: 1) defect-free formation of ultrasmall TPV holes with diameters of 15 $\mu{\rm m}$ at 27- $\mu{\rm m}$ pitch and 2) TPV metallization with copper. The fabricated TPVs in ultrathin glass showed a good model to hardware correlation of signal transmission with insertion loss ${ at 20 GHz. The results in this paper suggest that the 3-D interposer concept can be a simpler alternative to 3-D IC stacking with TSVs to achieve high bandwidth between the logic and memory devices.