Through Silicon Vias (TSVs) Technology for MEMS Packaging

Nowadays, three-dimensional (3D) integration has been widely applied in semiconductor and electronics industry. When 3D integration applied in MEMS (micro electromechanical system) packaging, it is possible to stack host MEMS chip/wafer with other chips/wafers (such as ASIC) to lower package profile and realize area array sensor system. In this paper, a miniaturized piezoresistive pressure sensor system with TSV structure has been designed to demonstrate the application of TSV in MEMS packaging. TSV in pressure sensor chip is designed to provide communication paths for electrical signals. Cu/Sn bump is electroplated after exposing TSV from backside and backside metallurgy. Signal read-out chip contains redistribution circuits and Au studs. The pressure sensor chip and signal read-out chip are flip chip bonded using Au-Sn eutectic bonding. To realize this pressure sensor system, a systematic process flow including piezoresistors fabrication and circuits patterning, TSV process, flip chip bonding, polymer hermetic sealing is designed and implemented experimentally.

This paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

In this paper, we show the advantages of 3-D stacked through silicon via (TSV) in high chip density package in aspect of wideband and low power distribution network (PDN) impedance. We selected large size (80 μm) and large pitch (200 μm) TSV with thick silicon substrate (Si, 80 μm, aspect ratio =1) for on-chip PDN, and compared two total PDN impedances of a PDN with TSVs and a PDN with wire-bondings depending on number of stacked chips from 2 to 10 on a single package. PDN impedance with TSVs includes total capacitance and inductance of TSV and 20 mm × 20 mm package substrate. PDN impedance with wire-bondings shows total capacitance and inductance of wire-bondings and same size package substrate. PDN impedance with TSVs has lower levels with wide bandwidth from 10 MHz to 5 GHz except serial resonance frequency range of the package substrate around 350 MHz. In low frequency range from 10 MHz to 350 MHz, total capacitance of a PDN with TSVs is larger than that of a PDN with wire-bonding because of 0.1 μm thickness silicon oxide (Si02) for blocking DC leakage from TSV to Si substrate. Over 350 MHz, total inductance of a PDN with TSVs is smaller than that of a PDN with wire-bonding because TSV is the smallest electrical path from top surface of stacked chips to the package PDN. The effectiveness of lowering total PDN impedance is better when the number of stacked chips is growing because total length of TSVs is linearly increased with factor 1 while total length of wire-bonding is done with factor √2.

Increasing demand for new and more advanced electronic products, with smaller form factor and superior functionality and performance, while reducing the cost, has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies. 3D packaging, using z-axis through silicon via (TSV) stacking concept has been and continues to be investigated by many of the semiconductor manufacturers and research institutes and is believed to be one of the most promising, if not the most promising concept that could successfully address the limitations of today's packaging technologies. There is a continuous increase of interest in development and study of applicability of this new chip stacking approach to existing and future devices; currently, more than fifty companies worldwide are involved in some sort of 3D TSV packaging developments. There are several steps involved in 3D chip stacking using TSV technology. Each of these steps requires different techniques, materials and processes, applications that have to be well understood and integrated in order to successfully be applied. This paper will address various electrodeposition processes applied to form 3D interconnects, from TSV deposition, which is the main metallization step that stays at the hearth of this new technology, to other metallization steps for additional connections, such as bumping and redistribution layers, already well known and applied processes in current wafer level packaging (WLP) applications. Advantages and difficulties associated with each of these technologies, with more focus on 3D vertical integration using TSV copper interconnect, including the approaches taken to overcome them, will be presented. Deposition conditions for bumping were optimized in order to enable higher deposition rates. For other through- mask applications, such as redistribution lines (RDL), the complexity of the pattern, deposition rate, chemical formulation and process parameters were found to have a significant effect on within-die (WID) thickness distribution. In case of WLP structures of thick metal and high aspect ratios, seed layer uniformity proved to be essential for achieving void-free deposition. Void-free structures, especially for high aspect ratio vias seeded with dry methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), seem difficult to obtain. New approaches, such as seed layer repair (SLE) or direct on barrier electrodeposition (DOB) can provide superior uniformity and coverage of the conductive layer, necessary for a uniform nucleation of copper electrodeposition process along the entire sidewall of the via, at significantly lower costs. This paper will present TSV structures obtained with wet chemical processes applications for both seed layer and via filling. Besides seed layer uniformity, additional factors were identified to also be critical for successfully filling deep vias. They are: via profile, wettability of vias, superior performance of chemistries and high performance equipment. By selecting the most appropriate deposition methods and optimizing the chemical formulations together with the process parameters, void-free TSV structures can be obtained.

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced multichip modules. This technology overcomes the resistance-capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense Z-axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO 2 , the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO 2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO 2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.

In this paper a low temperature ‘via-last’ technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the design of the TSV will be presented and a first approach of a design rule definition for TSV will be introduced. The alignment strategy will be also presented, and specific patterns to succeed front side to back side alignment will be described. In a second part the steps of the Through Silicon Vias (TSV) technology will be presented: glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like double side lithography, silicon deep etching, silicon side wall insulation, vias metallization and final bumping. A special focus will be done on this paper on the TSV metallization step and especially on the chemical seed layer etching. A study has been achieved in this project in order to optimize this part of the process and the results will be shown. Then, morphological and electrical characterizations of the via-last technology will be presented and discussed. Finally, a picture obtained with the TSV CMOS Image Sensor (TSV CIS) will be shown.

This study presents a double-layer atom chip that provides users with increased diversity in the design of the wire patterns and flexibility in the design of the magnetic field. It is more convenient for use in atomic physics experiments. A negative photoresist, SU-8, was used as the insulating layer between the upper and bottom copper wires. The electrical measurement results show that the upper and bottom wires with a width of 100 µm can sustain a 6 A current without burnout. Another focus of this study is the double-layer atom chips integrated with the through silicon via (TSV) technique, and anodically bonded to a Pyrex glass cell, which makes it a desired vacuum chamber for atomic physics experiments. Thus, the bonded glass cell not only significantly reduces the overall size of the ultra-high-vacuum (UHV) chamber but also conducts the high current from the backside to the front side of the atom chip via the TSV under UHV (9.5 × 10−10 Torr). The TSVs with a diameter of 70 µm were etched through by the inductively coupled plasma ion etching and filled by the bottom-up copper electroplating method. During the anodic bonding process, the electroplated copper wires and TSVs on atom chips also need to pass the examination of the required bonding temperature of 250 °C, under an applied voltage of 1000 V. Finally, the UHV test of the double-layer atom chips with TSVs at room temperature can be reached at 9.5 × 10−10 Torr, thus satisfying the requirements of atomic physics experiments under an UHV environment.

Simulation and fabrication of two Cu TSV electroplating methods for wafer-level 3D integrated circuits packaging

Void growth in through silicon vias (TSVs) has been imaged by X-ray microscope without physical cross sectioning. In additional, a finite element stress modeling is used to study the stress-assisted void growth. Fabrication of through silicon vias (TSVs) is challenging and often hampered by the presence of seam-line or voids inside the TSVs as pre-existing void. Annealing these TSVs induces large hydrostatic stress gradient distribute around the pre-existing void. This hydrostatic stress gradient is the driving forces for the vacancies to diffuse to the pre-existing void region and causing void growth. Because physical cross sectioning of TSVs is not required for the 8KeV lab-based X-ray microscope, the same TSVs can be imaged before and after annealing. Void growth is observed at the pre-existing void location after annealing in TSVs with 5μm in diameter and 26 μm of depth. Stresses in a copper-filled TSV with a pre-existing void were simulated by finite element methods and will be presented. The maximum of hydrostatic stress gradient is found to be around the void when cool down from annealing temperature to room temperature. The comparison between simulated results and experimental data show that void growth in TSV is stress-assisted, where vacancies diffuse and coalesce at the void as a result of the hydrostatic stress gradient.

Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs. TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e− mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.

In this paper, we design a new program to achieve carbon nanotubes through silicon vias (TSV) interconnects compatible with CMOS technology using an auxiliary TSV structures and laser local heating method. Auxiliary TSV structures are made by two wafers. One wafer is etched into ups and downs structures and then deposited SiN x and SiO 2 film. The other one is made into TSV structures by deep silicon etching, depositing thin film and wafer thinning and polish. Two wafers are bonded together by patterned BCB (Benzocyclobutene). For the entire device structures, we use FDTD solutions software to simulate infrared optical properties of SiN x . SiN x film layer can absorb 10.6 µm infrared laser strongly. Thermal simulation of geometrical model by COMSOL Multiphysics software shows well temperature compatibility. It turns out the program is compatible with current CMOS processes. Using a laser local heating method, we have studied the local growth of carbon nanotubes. Carbon nanotubes grown in TSVs are sparse, intertwined and have a poor morphology; the reason for this is that TSVs' geometric sizes limit gases flows. Carbon nanotubes interconnect still need further study.

Through Silicon vias (TSVs) are a key breakthrough in 3D technology to shorten global interconnects and enable the heterogeneous integration. However, TSVs also introduce an important source of noise coupling arising from electrical coupling between TSVs and the active devices. This paper investigates the TSV noise coupling to active devices including both FinFETs and planar transistors based on two-port S-parameter measurements up to 40 GHz. The measurements clearly show that nFinFETs have better noise coupling immunity than planar nNMOSFETs. The dominant coupling mechanisms were also identified for both types of active devices. Moreover, calibrated TCAD models were developed. We show that via-last TSV architectures with thick liners (“donut TSVs”) and scaled TSV diameters reduce the noise coupling to active devices. Finally, both coupling and stress induced saturation current variations as a function of TSV to active devices distance were investigated. This allows us to propose a novel model for the TSV Keep Out Zone (KOZ) including electromagnetic coupling effects.

Today 3D integration based on through silicon vias (TSV) is a well-accepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. According to the ITRS road map [1] there is a variety of reasons for application of 3D integration, such as miniaturization, improved circuit performance, lower power consumption and heterogeneous integration. World-wide, several full 3D process flows have been demonstrated. However, there is a strong demand for considering the behaviour and reliability of 3D-integrated systems [2]. Explicitly, the impact of 3D processes on the system, e.g. thermo-mechanical stresses, has to be evaluated before the implementation to production lines. A test chip for reliability evaluation of 3D TSV technologies was designed and fabricated by Fraunhofer EMFT. The 3D-integrated reliability test chip is a 3-level-stack with TSVs through a middle (2nd) device layer to connect structures on the bottom (1st) level with the top (3rd) level device. The layout is modular, so you can test basic assembly processing with the combination of level 1 with level 2 only and the influence of additional processing when adding level 3. For reliability testing, temperature cycling following the JEDEC standard was performed from −55 C ° to +150 °C (at a soak time of 5 minutes). Additionally, analysis was done by cross sectioning and reversed engineering. The 3D-integrated test chips were fabricated by application of Fraunhofer EMFT's TSV SLID technology. The applied 3D TSV process is based on intermetallic compound (IMC) bonding and TSV formation before stacking [3]. Reliability issues related to thermo-mechanical stress caused by the 3D integration process have to be considered. Failures of 3D integrated systems caused by TSV formation and the permanent bonding process were analysed by a novel high rate milling Focussed Ion Beam equipment. Figure 1 schematically shows the application of the novel FIB analysis technique for the areas of interest (IMC bond, TSV cross sections). Compared to classical FIB systems, the new equipment allows to remove material significantly faster while maintaining good resolution at low beam currents, important for the subsequent analysis. Cross sections of the 3-layer stack are shown in Figure 2. The merits of the novel plasma FIB and the resulting failure analysis will be discussed in detail.

Thermal issue is the leading design constraint for 3-D stacked integrated circuits (ICs) and through silicon vias (TSVs) are used to effectively reduce the temperature of 3-D ICs. Normally, TSV is considered as a good thermal conductor in its vertical direction, and its vertical thermal resistance has been well modeled. However, lateral heat transfer of TSVs, which is also important, was largely ignored in the past. In this paper, we propose an accurate physics-based model for lateral thermal resistance of TSVs in terms of physical and material parameters, and study the conditions for model accuracy. For TSV arrays or farm, we show that the space or pitch between TSVs has a significant impact on TSV thermal behavior and should be properly considered in the TSV models. The proposed lateral thermal resistance model is fully compatible with the existing modeling approaches, and thus we could build a more accurate complete TSV thermal model. The new TSV thermal model can be easily integrated into a finite difference (FD) based thermal analysis framework to improve analysis efficiency. The accuracy of the model is validated against a commercial finite element tool-COMSOL. Experimental results show that the improved TSV thermal model (with proposed lateral thermal model) could greatly improve the accuracy of FD method in thermal simulation comparing with the existing method.