Noise coupling between TSVs and active devices: Planar nMOSFETs vs. nFinFETs

Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

Through silicon via (TSV) based 3-dimensional integrated circuit (3D IC) has become the key solution to satisfy continuously increasing demands for small form factor, wide bandwidth, high performance, and low power consumption on electronic devices. However, there still remain several challenges to be solved; one of the most significant issues in 3D IC is TSV to active circuit noise coupling. In this paper, we analyzed the noise coupling between TSV and LC-VCO, which is an important component in RF communication system. When TSV is located near LC-VCO, the noise can easily travel through silicon substrate to the body of MOSFETs in LC-VCO. The noise coupling mechanisms of TSV to PMOS and NMOS are analyzed by voltage transfer functions in frequency-domain obtained by 3D electromagnetic solver simulation. The voltage transfer function between TSV and MOS is analyzed under variations of several physical parameters to clarify the tendencies of noise coupling. In addition, the noise coupling effect on PMOS and NMOS in LCVCO are investigated and compared in terms of sensitivity, such as phase noise.

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO 2 , the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO 2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO 2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.

Although a through-silicon via (TSV) is widely used in three-dimensional integrated circuit systems, one of its major design challenges is noise coupling between TSVs and active devices. This paper investigates noise coupling between TSVs and active devices for 20/14-nm technology nodes. The effect of variations of structural parameters on noise coupling was examined using a three-dimensional full-wave electromagnetic field solver and its result was explained. Additionally, transient analysis on coupling noise was conducted with Synopsys TCAD. Furthermore, a combined strategy employing doped signal TSVs and ‘bare’ ground TSVs was proposed and compared with conventional signal/ground schemes. Demonstrated to improve noise isolation effectively, the proposed strategy is inherently advantageous to circuits of advanced technology nodes compared with other noise isolation schemes, for it demands no modification of the original circuit design, placement and routing.

Through silicon vias (TSVs) provide advanced vertical interconnections solutions for system-in-package (SiP) (such as chip to chip, chip to wafer, and wafer to wafer stacking), wafer-level packaging, interposer packaging. At present the shortest electrical path (vertical electrical feed through) between two sides of a silicon chip is one of the important applications. In order to achieve high density and high performance package, TSVs technology has been developed. And for three-dimensional (3D) MEMS (Microelectromechanical System) packaging, TSVs are the most important enabling technology. In this paper, some advantages of TSVs technology are described, and process flow of TSVs module is introduced firstly. Subsequently, a novel electricity test method of Non-Ideal Planes for TSVs is introduced. Finally, many critical issues and challenges of TSVs are reviewed.

Void growth in through silicon vias (TSVs) has been imaged by X-ray microscope without physical cross sectioning. In additional, a finite element stress modeling is used to study the stress-assisted void growth. Fabrication of through silicon vias (TSVs) is challenging and often hampered by the presence of seam-line or voids inside the TSVs as pre-existing void. Annealing these TSVs induces large hydrostatic stress gradient distribute around the pre-existing void. This hydrostatic stress gradient is the driving forces for the vacancies to diffuse to the pre-existing void region and causing void growth. Because physical cross sectioning of TSVs is not required for the 8KeV lab-based X-ray microscope, the same TSVs can be imaged before and after annealing. Void growth is observed at the pre-existing void location after annealing in TSVs with 5μm in diameter and 26 μm of depth. Stresses in a copper-filled TSV with a pre-existing void were simulated by finite element methods and will be presented. The maximum of hydrostatic stress gradient is found to be around the void when cool down from annealing temperature to room temperature. The comparison between simulated results and experimental data show that void growth in TSV is stress-assisted, where vacancies diffuse and coalesce at the void as a result of the hydrostatic stress gradient.

In this paper, we show the advantages of 3-D stacked through silicon via (TSV) in high chip density package in aspect of wideband and low power distribution network (PDN) impedance. We selected large size (80 μm) and large pitch (200 μm) TSV with thick silicon substrate (Si, 80 μm, aspect ratio =1) for on-chip PDN, and compared two total PDN impedances of a PDN with TSVs and a PDN with wire-bondings depending on number of stacked chips from 2 to 10 on a single package. PDN impedance with TSVs includes total capacitance and inductance of TSV and 20 mm × 20 mm package substrate. PDN impedance with wire-bondings shows total capacitance and inductance of wire-bondings and same size package substrate. PDN impedance with TSVs has lower levels with wide bandwidth from 10 MHz to 5 GHz except serial resonance frequency range of the package substrate around 350 MHz. In low frequency range from 10 MHz to 350 MHz, total capacitance of a PDN with TSVs is larger than that of a PDN with wire-bonding because of 0.1 μm thickness silicon oxide (Si02) for blocking DC leakage from TSV to Si substrate. Over 350 MHz, total inductance of a PDN with TSVs is smaller than that of a PDN with wire-bonding because TSV is the smallest electrical path from top surface of stacked chips to the package PDN. The effectiveness of lowering total PDN impedance is better when the number of stacked chips is growing because total length of TSVs is linearly increased with factor 1 while total length of wire-bonding is done with factor √2.

Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs. TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e− mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.

In this paper, we design a new program to achieve carbon nanotubes through silicon vias (TSV) interconnects compatible with CMOS technology using an auxiliary TSV structures and laser local heating method. Auxiliary TSV structures are made by two wafers. One wafer is etched into ups and downs structures and then deposited SiN x and SiO 2 film. The other one is made into TSV structures by deep silicon etching, depositing thin film and wafer thinning and polish. Two wafers are bonded together by patterned BCB (Benzocyclobutene). For the entire device structures, we use FDTD solutions software to simulate infrared optical properties of SiN x . SiN x film layer can absorb 10.6 µm infrared laser strongly. Thermal simulation of geometrical model by COMSOL Multiphysics software shows well temperature compatibility. It turns out the program is compatible with current CMOS processes. Using a laser local heating method, we have studied the local growth of carbon nanotubes. Carbon nanotubes grown in TSVs are sparse, intertwined and have a poor morphology; the reason for this is that TSVs' geometric sizes limit gases flows. Carbon nanotubes interconnect still need further study.

This paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

In this paper a low temperature ‘via-last’ technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the design of the TSV will be presented and a first approach of a design rule definition for TSV will be introduced. The alignment strategy will be also presented, and specific patterns to succeed front side to back side alignment will be described. In a second part the steps of the Through Silicon Vias (TSV) technology will be presented: glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like double side lithography, silicon deep etching, silicon side wall insulation, vias metallization and final bumping. A special focus will be done on this paper on the TSV metallization step and especially on the chemical seed layer etching. A study has been achieved in this project in order to optimize this part of the process and the results will be shown. Then, morphological and electrical characterizations of the via-last technology will be presented and discussed. Finally, a picture obtained with the TSV CMOS Image Sensor (TSV CIS) will be shown.

Thermal issue is the leading design constraint for 3-D stacked integrated circuits (ICs) and through silicon vias (TSVs) are used to effectively reduce the temperature of 3-D ICs. Normally, TSV is considered as a good thermal conductor in its vertical direction, and its vertical thermal resistance has been well modeled. However, lateral heat transfer of TSVs, which is also important, was largely ignored in the past. In this paper, we propose an accurate physics-based model for lateral thermal resistance of TSVs in terms of physical and material parameters, and study the conditions for model accuracy. For TSV arrays or farm, we show that the space or pitch between TSVs has a significant impact on TSV thermal behavior and should be properly considered in the TSV models. The proposed lateral thermal resistance model is fully compatible with the existing modeling approaches, and thus we could build a more accurate complete TSV thermal model. The new TSV thermal model can be easily integrated into a finite difference (FD) based thermal analysis framework to improve analysis efficiency. The accuracy of the model is validated against a commercial finite element tool-COMSOL. Experimental results show that the improved TSV thermal model (with proposed lateral thermal model) could greatly improve the accuracy of FD method in thermal simulation comparing with the existing method.

Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk noise between the neighboring TSVs, and result in the extra delay and the deterioration of signal integrity. For a 3 × 3 TSV array, the severity of crosstalk noise in the center victim TSV is classified into 11 levels, which is defined as 0C to 10C from low noise to high noise, depending on the combinations of the digital patterns applied to the TSV array. An enhanced code based on the Fibonacci number system (FNS) to suppress the crosstalk noise below 6C level is proposed, in which both the redundancy of numbers and the nonuniqueness of Fibonacci-based binary codeword are utilized to search the proper codeword. Experimental results show that the proposed technique decreases about 22% latency of TSVs comparing with the worst crosstalk cases. This technique is applicable in the large-scale TSV array for it has a quasi-linear hardware overhead, and its system overhead is less than that of the 3-D 4-LAT counterpart if the data width is greater than 18, and it has good usability for it consumes less power per TSV and achieves lower bit error rate at the interested frequency range comparing with that of the original FNS coding technique.

Through silicon vias (TSV) are an enabler for high performance Three Dimensional Integrated Circiuts (3DIC). TSVs are used for signal, power and ground lines in 3DICs. TSVs used to carry signals can induce noise in nearby circuitry and in those instances shielding is required. Traditional shielding is composed of guard rings surrounding the signal TSVs or if the signal is differential in nature, a careful arrangement of TSVs carrying the differential signals can aid in noise reduction. In the guard ring scenario, the guard rings are typically tied to ground. This paper proposes a technique for energy scavenging utilizing the guard rings for shielding TSVs. Energy absorbed by the guard rings can be stored for later use by the system. This paper examines the feasibility of configuring the guard rings to charge a decoupling capacitor instead of shunting energy to ground. It is shown that the decoupling capacitor can be charged using this method and that under certain conditions, the overall power of the system can be reduced by 4% to 15%