Early Layout Design Exploration in TSV-based 3D Integrated Circuits

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

Through silicon via (TSV) based 3-dimensional integrated circuit (3D IC) has become the key solution to satisfy continuously increasing demands for small form factor, wide bandwidth, high performance, and low power consumption on electronic devices. However, there still remain several challenges to be solved; one of the most significant issues in 3D IC is TSV to active circuit noise coupling. In this paper, we analyzed the noise coupling between TSV and LC-VCO, which is an important component in RF communication system. When TSV is located near LC-VCO, the noise can easily travel through silicon substrate to the body of MOSFETs in LC-VCO. The noise coupling mechanisms of TSV to PMOS and NMOS are analyzed by voltage transfer functions in frequency-domain obtained by 3D electromagnetic solver simulation. The voltage transfer function between TSV and MOS is analyzed under variations of several physical parameters to clarify the tendencies of noise coupling. In addition, the noise coupling effect on PMOS and NMOS in LCVCO are investigated and compared in terms of sensitivity, such as phase noise.

Through Silicon vias (TSVs) are a key breakthrough in 3D technology to shorten global interconnects and enable the heterogeneous integration. However, TSVs also introduce an important source of noise coupling arising from electrical coupling between TSVs and the active devices. This paper investigates the TSV noise coupling to active devices including both FinFETs and planar transistors based on two-port S-parameter measurements up to 40 GHz. The measurements clearly show that nFinFETs have better noise coupling immunity than planar nNMOSFETs. The dominant coupling mechanisms were also identified for both types of active devices. Moreover, calibrated TCAD models were developed. We show that via-last TSV architectures with thick liners (“donut TSVs”) and scaled TSV diameters reduce the noise coupling to active devices. Finally, both coupling and stress induced saturation current variations as a function of TSV to active devices distance were investigated. This allows us to propose a novel model for the TSV Keep Out Zone (KOZ) including electromagnetic coupling effects.

In this paper, we propose a multilevel multilayer partitioning algorithm for 3D ICs application. The algorithm is based on the multilevel framework to coarsen the netlist successively. A multilayer partitioning procedure is applied on each level of partition during the un-coarsening process. The objective is to minimize the total number of Through Silicon Via (TSV) while observing the area constraint for each layer. The area of each layer is the summation of circuit area and TSV area. The partitioning algorithm is customized for the structure of 3D ICs. We utilize a FM-like data structure and identify eight critical net distributions such that after a cell move, the program can update gains very effectively. The experimental results show that the proposed algorithm can effectively produce good results with small numbers of TSV, area overhead, and area coefficient of variation for the tested industrial cases. The average area overhead is only 1.84% that shows the average white space is very small. The average area coefficient of variation is only 2.61% that shows area distribution of all layers is very uniform. The results also achieve the best average value for both number of TSVs and chip area, compared to all participating teams in “Design Partition for 3D ICs” problem in the IC/CAD 2009 contest in Taiwan.

The advent of 3D IC technology facilitates fabrication of large logic circuits on low area yet high performance chips. For a 3D IC, placement followed by assignment of Through-Silicon-Vias (TSV)s is a challenging problem involving various issues like inter-layer wirelength, power density, congestion and variation in surrounding carrier mobility. Each of the existing techniques for placement of TSVs deals only with a subset of these issues. In this paper, we propose an evolutionary approach MO_TSV to handle this multi-objective optimization problem. Although this method has some similarity with the framework of NSGA-II, several variations have been incorporated so that, on exploration of variety of non-dominated solutions the search process converges to a near-optimum solution in reasonable time. Experimental results on ISCAS'85 and ISCAS'89 benchmarks yield solution quality aswell as convergence times, which are encouraging.

Core based three-dimensional(3D) integrated circuits (ICs) design is an emerging field of semiconductor industry that promises greater number of devices on chip, increased performance and reduced power consumption. But due to scaling in technology features these chips are more complex and hence testing of these 3D ICs is a challenging task. This paper follows a P1500-style wrapper design for 3D ICs using through silicon vias (TSVs) for testing purpose. It is assumed that the core elements are distributed over several layers of the ICs. As the number of available TSVs are limited due to small chip area, this work is intended to design balanced wrapper chains using available TSVs. In this work we have proposed a polynomial time algorithm of O(N) to design the test wrapper. The results are presented based on the ITC'02 SOC test benchmarks and compared with prior work. Obtained results show that our algorithm provides better utilization of TSVs compared to the work presented in.

Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of the major challenges of 3D integration. In this paper, different materials for the cores of the vias and the interposers are investigated to find the best possible combination that can reduce crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored glass and silicon as interposer materials. The simulation results indicate that glass is the best option as interposer material although silicon interposer has some distinct advantages. For via cores three materials — copper (Cu), tungsten (W) and Cu-W bimetal are considered. From the analysis it can concluded that W would be better for high frequency applications due to lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be in between Cu and W. However, W has a thermal expansion coefficient close to silicon. Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission coefficient and crosstalk in the vias.

Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs. TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e− mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.

Through silicon vias (TSV) are an enabler for high performance Three Dimensional Integrated Circiuts (3DIC). TSVs are used for signal, power and ground lines in 3DICs. TSVs used to carry signals can induce noise in nearby circuitry and in those instances shielding is required. Traditional shielding is composed of guard rings surrounding the signal TSVs or if the signal is differential in nature, a careful arrangement of TSVs carrying the differential signals can aid in noise reduction. In the guard ring scenario, the guard rings are typically tied to ground. This paper proposes a technique for energy scavenging utilizing the guard rings for shielding TSVs. Energy absorbed by the guard rings can be stored for later use by the system. This paper examines the feasibility of configuring the guard rings to charge a decoupling capacitor instead of shunting energy to ground. It is shown that the decoupling capacitor can be charged using this method and that under certain conditions, the overall power of the system can be reduced by 4% to 15%

3D IC technologies are now approaching the innovation and business activities of semiconductor industries. 3D IC can be heterogeneous from different chip, interposer or substrate to integrate into a single package by using through silicon via (TSV) technique. With increasing functionality and performance at minimum cost and power dissipation, wide I/O memory VLSI technologies are being aggressively scaled to meet this demand. Stack memory chips using TSV technique will lead to increase a significant manufacturing challenge for semiconductor industries. TSV formation and interconnected reliability on the intermetallic compound (IMC) between the metal-metal bounded micro-bumps are crucial for 3D IC technologies. As the number and power of IC increases, lots of heat will be generated and, in turn raises the junction temperature. This will greatly deteriorate the performance of IC. Heat dissipation for 3D IC, when the power density exceeds 100W/cm2, is an important design concern before marketing. In this paper, high density TSV formed by an ultrafast pico-second laser to evaluate the behavior between manufacturing process and silicon material is presented. In addition, thermal management using finite element analysis to predict the reliability of TSV model is demonstrated.

In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.

Through-silicon via (TSV) based 3D integrated circuit (IC) testing is promising area to the researchers in modern day semiconductor industry. The manufacturing of 3D ICs may produce TSV defects which reduce yield. Recent work has proposed grouping of functional and redundant TSVs such that the faulty functional TSVs are supported by redundant TSVs and multiplexers (MUXs) are used to implement that group. This paper proposes grouping of functional and redundant TSVs such that a functional TSV is supported by redundant TSVs of other groups. We have presented an algorithm that finds the best grouping of functional and redundant TSVs such that maximum recovery of functional TSVs can be achieved with a given number of MUXs.

LC resonant clock is an attracting option for low power on-chip clock distribution designs. However, a major limiting factor to its implementation is the large area overhead due to the conventional spiral inductors. On the other hand, idle through-silicon-vias (TSVs) in three-dimensional integrated circuits (3D ICs) can form vertical inductors with minimal footprint and little noise coupling with horizontal traces, particularly suitable for the application of LC resonant clock. However, due to the strict constraints on the location of idle TSVs, the use of the TSV inductor is limited by the constrained choices of its location, inductance and quality factor. Moreover, these TSV inductors can be in any orientation with any distance apart, thereby causing complicated coupling effects. In this paper, we present a novel scheme to opportunistically use idle TSVs to form inductors in LC resonant clock of 3D ICs for maximum power reduction. We formulate the problem and devise a greedy algorithm to efficiently solve it. Experimental results on a few industrial designs show that compared with the conventional resonant clock designs using spiral inductors, our scheme with TSV inductors can reduce the inductor footprint by up to 6.30x with the same power consumption. Especially these TSV inductors are formed by existing idle TSVs so they essentially come for free. To the best of the authors' knowledge, this is the very first work to apply TSV inductors to the resonant CDN.

Manufacturing of three-dimensional (3D) IC chips is become executable nowadays with the furtherance in fabrication engineering. However, the process of designing and testing of tools in this regards are even if non-autumnal. One of the main challenges is to reduce the total time for testing of such chips. In order to make a reduction in the test application time, the wrapper design must be balanced such that all scan chain lengths are almost of equal length. Minimization of the scan test time is possible with the help of above-proposed work with the available numeral of through silicon vias (TSVs). The Verilog coding intended for the proposed implementation has been done using Cadence tool to analyze power and delay.