Etching process development for 3D wafer level via last TSV package

This paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

The demand from digital mobile industry is pushing the development of smaller, more compact and more effective electronic device likes SiP, RFID and etc in the past few years. For a higher performance and energy saving solution, the development of TSV (Through Silicon Via) package has been sped up for the past few years. In China, the development of TSV and BSI (Backside illumination) technology for high pixel camera module used in the smart phone is progressing rapidly since the past one year. For TSV and BSI device, the requirement of grinding process is different from the normal grinding system used in the backend assembly process. In this paper, the author would like to discuss about the requirement needed in this technology.

Low cost wafer-level chip-scale vacuum packaging (WLCSVP) imposes unique constraints on potential implementation of through-silicon vias (TSVs). A WLCSVP requires a relatively thick substrate to prevent mechanical failure. Two approaches for integrating TSVs in thick silicon wafers have been successfully demonstrated. Both approaches enable TSV formation from the backside of a device wafer and are compatible with the requirements of subsequent packaging operations. We achieved low contact resistance between TSVs and frontside Ti/Cu and Al metallization, while demonstrating high isolation resistance and high TSV yield.

Increasing demand for new and more advanced electronic products, with smaller form factor and superior functionality and performance, while reducing the cost, has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies. 3D packaging, using z-axis through silicon via (TSV) stacking concept has been and continues to be investigated by many of the semiconductor manufacturers and research institutes and is believed to be one of the most promising, if not the most promising concept that could successfully address the limitations of today's packaging technologies. There is a continuous increase of interest in development and study of applicability of this new chip stacking approach to existing and future devices; currently, more than fifty companies worldwide are involved in some sort of 3D TSV packaging developments. There are several steps involved in 3D chip stacking using TSV technology. Each of these steps requires different techniques, materials and processes, applications that have to be well understood and integrated in order to successfully be applied. This paper will address various electrodeposition processes applied to form 3D interconnects, from TSV deposition, which is the main metallization step that stays at the hearth of this new technology, to other metallization steps for additional connections, such as bumping and redistribution layers, already well known and applied processes in current wafer level packaging (WLP) applications. Advantages and difficulties associated with each of these technologies, with more focus on 3D vertical integration using TSV copper interconnect, including the approaches taken to overcome them, will be presented. Deposition conditions for bumping were optimized in order to enable higher deposition rates. For other through- mask applications, such as redistribution lines (RDL), the complexity of the pattern, deposition rate, chemical formulation and process parameters were found to have a significant effect on within-die (WID) thickness distribution. In case of WLP structures of thick metal and high aspect ratios, seed layer uniformity proved to be essential for achieving void-free deposition. Void-free structures, especially for high aspect ratio vias seeded with dry methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), seem difficult to obtain. New approaches, such as seed layer repair (SLE) or direct on barrier electrodeposition (DOB) can provide superior uniformity and coverage of the conductive layer, necessary for a uniform nucleation of copper electrodeposition process along the entire sidewall of the via, at significantly lower costs. This paper will present TSV structures obtained with wet chemical processes applications for both seed layer and via filling. Besides seed layer uniformity, additional factors were identified to also be critical for successfully filling deep vias. They are: via profile, wettability of vias, superior performance of chemistries and high performance equipment. By selecting the most appropriate deposition methods and optimizing the chemical formulations together with the process parameters, void-free TSV structures can be obtained.

Through silicon vias (TSVs) provide advanced vertical interconnections solutions for system-in-package (SiP) (such as chip to chip, chip to wafer, and wafer to wafer stacking), wafer-level packaging, interposer packaging. At present the shortest electrical path (vertical electrical feed through) between two sides of a silicon chip is one of the important applications. In order to achieve high density and high performance package, TSVs technology has been developed. And for three-dimensional (3D) MEMS (Microelectromechanical System) packaging, TSVs are the most important enabling technology. In this paper, some advantages of TSVs technology are described, and process flow of TSVs module is introduced firstly. Subsequently, a novel electricity test method of Non-Ideal Planes for TSVs is introduced. Finally, many critical issues and challenges of TSVs are reviewed.

Simulation and fabrication of two Cu TSV electroplating methods for wafer-level 3D integrated circuits packaging

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.

The current market driver for semiconductor package technology is to provide more functionality and improve performance without increasing package size. Vertically configured 3D package technology addresses this issue for a broad number of enterprise products. Initially, the 3D package contained two or more semiconductor die elements mounted on top of one another most often interconnected using a common substrate interposer. Adapting through silicon via (TSV) technology for die-on-die interface on the other hand has the potential to further improve both package performance and package assembly efficiency. Progress in this area has accelerated through the cooperation and joint development programs between a number of government, industry and technical universities. An early high volume application for TSV was for the small CMOS image sensors used in wireless handsets to enable the vertical joining of the sensor and related logic element. Although the TSV process is touted as the 'next big thing' in semiconductor packaging, capabilities and methodologies for providing wafers and die elements for stacking currently vary a great deal between suppliers. Although TSV technology has the potential to revolutionize semiconductor packaging, it currently remains hostage to a very limited homogeneous family of products; MEMS, memory and image sensors. In addition, there are a number of processes and methodologies that are considered proprietary and may require licensing agreements and additional fees for their use. Industry roadmaps, however, continue to point toward the eventual use of TSV in developing new generations of high performance system-in-package products. What You Will Learn: This webinar will explore two basic approaches to TSV formation, via-first and via-last: Via-first integration forms very small via holes in the wafer during front-end processing. Via-last integration may occur before or after bonding wafers or joining individual die elements to one another (Die-on-Die). Due to the increased thickness of pre-joined die, the via-last process typically provides somewhat larger via holes than the via-first variation. Who Should View This Webinar: This Webinar has been developed specifically for product and circuit design professionals, systems engineers as well as assembly and test engineering specialists for OEM, ODM and EMS providers. About the presenter: Vern Solberg is a technical consultant for Invensas Corporation specializing in SMT and microelectronics design and manufacturing technology. Vern is a US delegate to the JISSO International Council (JIC) and is currently an active member of IEEE, SMTA, IMAPS and the IPC. He has served the industry for more than thirty years in areas related to both commercial and aerospace electronic products and is active as an author and educator. Solberg holds several patents for 3D semiconductor packaging innovations and is the author of Design Guidelines for Surface Mount and Fine-Pitch Technology and furnishes the 'Designers Notebook' column for SMT magazine. On Demand Webinar

Through Silicon Via (TSV) is a lead topic in interconnects and 3D integration research, mainly due to numerous anticipated advantages. However, several challenges must still be overcome if large scale production is to be achieved. In this work, we have studied effects of Bosch scallops concerning mechanical reliability for a specific TSV technology. We identified that the presence of scallops on the TSV wall modifies the stress distribution. The achieved results support experiments and give a better insight into the influence of scallops in an open TSV.

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced multichip modules. This technology overcomes the resistance-capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense Z-axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.

Through Silicon Via (TSV) technology has been a preferred and promising strategy to achieve the reliable interconnection for the integration of 3D IC. The temperature made some changes within the procedures of the manufacture of TSV and the adoption of chips because of the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials adopted within TSV structure, important thermal stress is going to be induced under the thermal load. The stresses are possible to cause different reliability problems. Dimension parameters are going to influence TSV’s thermal behaviors. For the purpose of optimizing the design of TSV, Cu-filled TSV’s numerical model had been set up for simulating and analyzing the influence of the thickness of SiO 2 , aspect ratio (AR), diameter and shape upon TSV thermal stress within the paper. The outcomes of the simulation present that the maximum of the areas of equivalent stress always happens at the bottom and top of the interface of Cu/SiO 2 . The aspect ratio’s influence on the equivalent stress is rather small when aspect ratio is more than 6 for vertical TSV. Vertical TSV with thicker SiO 2 layer may improve its reliability. However, the SiO 2 layer thickness does not have obvious influence for the inclined TSV upon equivalent stress.

3D technology is envisioned to offer advanced integration capabilities, enabling heterogeneous system integration and offering improved performance and reduced power consumption thanks the so-called Through Silicon Vias (TSVs). Nevertheless, 3D integration is facing strong thermal issues due to its higher power density and reduced heat dissipation properties. In previous studies, it has been often reported the use of TSV insertion techniques for thermal mitigation in 3D stacked circuits. However, due to the thin oxide layer isolating TSVs from silicon substrate, the expected thermal mitigation is actually not effective for the current TSV technologies. This paper firstly provides an analytical study to project the potential benefits and drawbacks of using TSVs for thermal mitigation. Detailed FEM simulations and experimental silicon data from a dedicated thermal test chip are then used to confirm the projections and demonstrate that TSVs may even increase the temperature of hotspots. This paper secondly reports the study of the thermal performance of multiple TSV arrays using thermal simulations for various system-level configurations, including a WideIO compatible 3D circuit. Similar results are obtained where, besides not alleviating thermal issues, TSVs may produce exacerbated hotspots. The results presented in this paper indicate that the use of additional area costly TSVs for thermal mitigation is not worthy.

Through Silicon Via (TSV) can be used to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1-3]</sup> . Via Reveal-a kind of wafer back side process moduleplays an important role in the successful implementation of TSV. In via-first and via-mid TSV integration flows, Si must be removed from the backside of the wafer to make contact with the bottom of the TSVs. This operation is performed using a mechanical grind followed by a reveal etching process. So in this paper, we will focus on the TSV reveal unit process. Firstly, we will briefly review TSV integration technology; Then a set of experiments is described which were used to select etch parameters to achieve the desired etching rate, selectivity and profile. Lastly we will show the results of TSV reveal using wet etching process. The proper composition of the HNO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HF/CH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> COOH(HNA) solutions, etching parameter, and TEOS deposited by proper temperature provide the necessary process control and etching selectivity that enable the use of higher throughput wet etch for TSV back etch.

TSV (Through Silicon Via) is a new method for 3D technology (IC integration). Different chips can be connected with the Cu line through silicon substrate. Via area is so deep (usually 100-300um) that we need thicker barrier and seed layer. The Cu plating is the key step in TSV flow. But we suffered TSV void issue in TSV ECD (Electro Chemical Deposition ) process for TSV seed layer poor condition impact .It is important to understand how to improve TSV Cu plating gap fill capability in order to develop TSV technology. In this paper, the barrier and seed layer performance improvement in TSV Cu plating is introduced, and then an effective approach to improve the TSV plating gap fill capability is demonstrated.

This paper presents a micromachined stress-free through silicon via (TSV) backend process for AlGaN/GaN-on-Si (1 1 1) platform-based devices, which was processed by assisted back grinding, chemical mechanical polishing, deep reactive ion etching (DRIE) and copper (Cu) electroplating for the TSV. The metal-filled TSV structure was formed to enhance thermal conduction from the frontend terminal to the backend terminal, especially the source region of the AlGaN/GaN-on-Si (1 1 1) platform-based RF power devices. At the end of a stress-free TSV dry etching process, we have changed RF power 600 W to 300 W to minimize thermal stress of the fabricated TSV electrode pad structure of the AlGaN/GaN-on-Si platform-based devices. Additionally, we have sputtered a multi-metal layer and electroplated Cu metal to interconnect a topside electrode to TSV. To protect the thinned TSV electrode pad structure from water pressure in a sawing process, we have covered photoresist (AZ4330RS) of 3.3 µm thickness on the top area of the structures. We confirmed that the proposed TSV formation method assisted by low-power operation DRIE and protection of the thinned TSV surface by using the thick photoresist is very effective to create minimally stressed TSV structures in AlGaN/GaN-on-Si platform-based devices. The improvement was proved by the yield of dice without bursting the pad structures on a 4 inch AlGaN/GaN-on-Si wafer.