Implementing TSV for 3D Semiconductor Packaging

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

Increasing demand for new and more advanced electronic products, with smaller form factor and superior functionality and performance, while reducing the cost, has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies. 3D packaging, using z-axis through silicon via (TSV) stacking concept has been and continues to be investigated by many of the semiconductor manufacturers and research institutes and is believed to be one of the most promising, if not the most promising concept that could successfully address the limitations of today's packaging technologies. There is a continuous increase of interest in development and study of applicability of this new chip stacking approach to existing and future devices; currently, more than fifty companies worldwide are involved in some sort of 3D TSV packaging developments. There are several steps involved in 3D chip stacking using TSV technology. Each of these steps requires different techniques, materials and processes, applications that have to be well understood and integrated in order to successfully be applied. This paper will address various electrodeposition processes applied to form 3D interconnects, from TSV deposition, which is the main metallization step that stays at the hearth of this new technology, to other metallization steps for additional connections, such as bumping and redistribution layers, already well known and applied processes in current wafer level packaging (WLP) applications. Advantages and difficulties associated with each of these technologies, with more focus on 3D vertical integration using TSV copper interconnect, including the approaches taken to overcome them, will be presented. Deposition conditions for bumping were optimized in order to enable higher deposition rates. For other through- mask applications, such as redistribution lines (RDL), the complexity of the pattern, deposition rate, chemical formulation and process parameters were found to have a significant effect on within-die (WID) thickness distribution. In case of WLP structures of thick metal and high aspect ratios, seed layer uniformity proved to be essential for achieving void-free deposition. Void-free structures, especially for high aspect ratio vias seeded with dry methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), seem difficult to obtain. New approaches, such as seed layer repair (SLE) or direct on barrier electrodeposition (DOB) can provide superior uniformity and coverage of the conductive layer, necessary for a uniform nucleation of copper electrodeposition process along the entire sidewall of the via, at significantly lower costs. This paper will present TSV structures obtained with wet chemical processes applications for both seed layer and via filling. Besides seed layer uniformity, additional factors were identified to also be critical for successfully filling deep vias. They are: via profile, wettability of vias, superior performance of chemistries and high performance equipment. By selecting the most appropriate deposition methods and optimizing the chemical formulations together with the process parameters, void-free TSV structures can be obtained.

Through silicon vias (TSVs) provide advanced vertical interconnections solutions for system-in-package (SiP) (such as chip to chip, chip to wafer, and wafer to wafer stacking), wafer-level packaging, interposer packaging. At present the shortest electrical path (vertical electrical feed through) between two sides of a silicon chip is one of the important applications. In order to achieve high density and high performance package, TSVs technology has been developed. And for three-dimensional (3D) MEMS (Microelectromechanical System) packaging, TSVs are the most important enabling technology. In this paper, some advantages of TSVs technology are described, and process flow of TSVs module is introduced firstly. Subsequently, a novel electricity test method of Non-Ideal Planes for TSVs is introduced. Finally, many critical issues and challenges of TSVs are reviewed.

This paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

To confirm the effectiveness of the via-last through silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer, we evaluated the metal contamination caused by this process. The metal contamination generated near the TSV was investigated by measuring the reverse-bias leakage current of n+/p diodes placed near the TSV. The TSV diameter was 6 µm and the n+/p diode size was 0.6 × 2 µm. The distance between the n+/p diodes and the TSV was 1-10 µm. The notching size was controlled by the etching time. The reverse bias leakage current was small regardless of the distance between the TSV and n+/p diode when the notching size was small (

New electronic devices with small size and low power consumption are in demand in recent years. Miniaturization and complex product are required in modern electronics for more functionality in the smaller electronic package. To overcome such issues, 3D packages or package on package (PoP) are introduced. The 3D packaging is stacking of chip on top of another which is emerging as a powerful technology that satisfies such integrated circuit (IC) package demands. A 3D package using through silicon vias (TSVs) has emerged as an effective technology for future interconnection requirements. The mismatch of coefficient of thermal expansion (CTE) of the SiO2 and copper used in TSV can induce a lot of thermal stresses. The stress developed at interfaces results in the interfacial delamination of TSV, which is mainly driven by a shear stress concentration at the point. The developed thermal stresses are critical for the thermo-mechanical reliability of the 3D package. In this paper, the effect of package structure on the failure metric of the 3D package has been studied. J-integral has been used to quantify the crack driving force. The crack is modeled at the TSV and BEOL (Back End of the Line) and the die-substrate thickness is varied and studied during chip attachment process and under thermal cycling load for optimizing the die and substrate thickness design [1]. Finite Element method have been used to analyze the thermo-mechanical stresses and fracture parameters in TSV structures 3D package. For this study, full field compact modeling methodology [2] has been leveraged for the ease of FEA using ANSYS Workbench 17.2. An optimized package assembly was obtained to reduce the crack driving energy at the TSV region and in the BEOL dielectric layer. A design approach has been proposed to mitigate brittle failure issues thus improving the thermo-mechanical reliability of the 3D package.

Nowadays, three-dimensional (3D) integration has been widely applied in semiconductor and electronics industry. When 3D integration applied in MEMS (micro electromechanical system) packaging, it is possible to stack host MEMS chip/wafer with other chips/wafers (such as ASIC) to lower package profile and realize area array sensor system. In this paper, a miniaturized piezoresistive pressure sensor system with TSV structure has been designed to demonstrate the application of TSV in MEMS packaging. TSV in pressure sensor chip is designed to provide communication paths for electrical signals. Cu/Sn bump is electroplated after exposing TSV from backside and backside metallurgy. Signal read-out chip contains redistribution circuits and Au studs. The pressure sensor chip and signal read-out chip are flip chip bonded using Au-Sn eutectic bonding. To realize this pressure sensor system, a systematic process flow including piezoresistors fabrication and circuits patterning, TSV process, flip chip bonding, polymer hermetic sealing is designed and implemented experimentally.

Through Silicon Via (TSV) is a lead topic in interconnects and 3D integration research, mainly due to numerous anticipated advantages. However, several challenges must still be overcome if large scale production is to be achieved. In this work, we have studied effects of Bosch scallops concerning mechanical reliability for a specific TSV technology. We identified that the presence of scallops on the TSV wall modifies the stress distribution. The achieved results support experiments and give a better insight into the influence of scallops in an open TSV.

Recently, the downsizing and high-performing semiconductor packages have been developed and 3D packaging has been spurred research into reliability of TSV (through silicon via) [l]-[9]. In conventional SiP (System in Package), several semiconductor chips had been arranged in a plate. It is difficult to correspond to downsizing and high-performing of electronic devices because that large area is occupied by the package. The semiconductor chips have been stacked and TSVs have been used to communicate between the chips in order to solve above problems. The 3D stacked structure which was developed by ASET (Association of Su per-Advanced Electronics Technologies) [10] is shown in Fig.1. TSV (copper) is electrode which passes through silicon chip and micro bump (copper) [11] is arranged between chips. Heat is generated in package due to operation of semiconductor device, and it has been reported that silicon is broken by thermal stress which is depend on temperature increment. In case of 3D-SIP, higher stress has to be considered in the most outer part of TSV and micro bump structure due to warp and mismatch of CTE (coefficient of thermal expansion) of material. Therefore simulations with detail model must be desired for more accurate evaluation of stresses in Si chips and TSVs. However it is difficult that all of TSVs and micro bumps in chips were modeled due to large number of numerical data even if the latest computing systems have been adopted.

3D Packaging Technologies and Applications, Latest Challenges and Supply Chain ActivitiesSemiconductor industry, for more than four decades, has rigorously followed Moore's Law in scaling down the CMOS technologies. Although several new materials and processes are being developed to address the challenges of future technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect is one the emerging options, considered today the most advanced technology, that could enable various heterogeneous integration. 3D Integration is not limited to the CMOS scaling in itself, it is rather based on bringing more functionalities by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive components) while reducing the form factor of the packaging. This functional diversification is also known as More-than-Moore. In addition, considering Known Good Die approach, each component of the 3D package could have a different manufacturer using different wafer sizes and node technology, thus bringing more complexity but also more opportunities and responsibilities to the supply chain. There are several business models identified, either using vertical integration or collaborative approach, if a dominant one will emerge or several tactics will co-exist, it is still remains a key question that will have to be answered. The supply chain interaction and key players will be addressed in this presentation, including current and future standardization needs. This is today a key for the manufacturing of advanced 3D devices. 3D integration is considered today a new paradigm for the semiconductor industry, since it will drive evolution for packages for the coming decades. Due to several advantages that TSV technology can bring, several platforms have started. 3D WLCSP, 2.5D interposers & 3DIC are the main platforms that will be studied in this paper. Market forecasts in terms of wafer starts, market revenue, segments and end-products as well as supply chain activities and major player interactions will be presented. The industry has enthusiastically been waiting for mass production of 3D ICs. Although some small level of production has already been reported, the adoption rate in high volume manufacturing (HVM) is still low due to unresolved challenges that the industry still needs to address. Process technology is not fully mature, there are still many challenges in bonding and de-bonding, testing as well as thermal management that have to be overcome. Furthermore, design tools have to be fully released to enable proper 3D integration design. Looking at the time to market it is foreseen that device such as the Hybrid Memory Cube, combining high-speed logic with multiple stacks of TSV bonded memories, will come into high volume production in 2014. This will definitely change the world of the memory market and will significantly speed up the adoption of 3D technologies. Technology roadmaps for 3D integration will also be included in the manuscript and reviewed during the presentation.

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced multichip modules. This technology overcomes the resistance-capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense Z-axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.

In this paper we present the process and electrical results of a 3D integration using through silicon vias (TSV). A flash memory chip has been directly connected to a processor die. The TSVs have been applied from the wafer front-side into a fully processed advanced CMOS 300 mm wafers using a via last approach. After dry etching the 20 by 107 μm holes into the substrate an isolation and barrier seed films are deposited and then filled with copper. The electrical connection between the pad level of the processor chips and the interface to the external connections is realized with a two level redistribution wiring. Subsequently the wafer is flipped, temporary bonded to a carrier wafer, thinned and the TSVs are connected from the wafer backside. Finally the flash chips are assembled to the controller die using a die-to-wafer (D2W) technique. Electrical tests have been conducted and a high yield after TSV processing and assembly determined. The isolation properties and electrical resistance was measured. The linear current in stress transistors was used to define a keep out zone.

Cu-filled through-silicon vias (TSVs) are an essential building block of 3D and 2.5D integrated chips. In the TSV-mid processing flow, which has emerged as an industry mainstream, one or more on-chip wiring levels are formed after the TSV Cu fill is completed, which exposes the fill to peak temperatures of up to 400 °C. Due to the higher coefficient of thermal expansion (CTE) of Cu than the surrounding silicon and dielectrics, the TSV fill protrudes above the level previously defined by the TSV chemical mechanical polishing (CMP) step. Even after returning to room temperature, the top of the TSV will not occupy the same space due to plastic deformation during the thermal treatment. This phenomenon is known as Cu protrusions, pumping, or popping. Excessive amounts of Cu protrusion present a risk to yields and reliability because the expansion can damage dielectrics and wiring above or adjacent to the TSVs. In this study, we report the underlying mechanisms as well as process remedies for Cu protrusions. The SEMATECH 5 um × 50 um TSV process and learning vehicle is used to conduct process split experiments comparing various plating chemistries, plating recipes, and post-plating anneal conditions. Stresses in the surrounding silicon are studied by micro-Raman, and a distinct signature distinguishing good from bad Cu protrusion behavior is identified. Cu material properties such as contamination, grain size, grain orientation, and strain may also influence the protrusion behavior; these factors are studied by micro-secondary ion mass spectroscopy (SIMS) and electron backscatter spectroscopy (EBSD). Our results shows that the choice of plating chemistry and subsequent optimized post-plating anneal are the main factors in suppressing Cu protrusions. Our best known method is able to reduce Cu protrusions to about 15 nm after typical thermal loads.

The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There is active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, there is increased in the demand for fine pitch copper pillar bumping due to the lower silicon node, chip size reduction and TSV technology. Fine pitch interconnections are required in 2.5D and 3DIC integration for the demands of electrical continuity and high performance. In the existing interconnection methods, solder micro bumps have received a great deal of attentions because of its low material and process cost [2]. The major difference of copper pillar FC bonding process comparing to traditional FC bonding process is the reduction of the solder volume on each solder bump. As a result, there is no advantage of self-alignment of the solder during solder reflow process. Flip-chip bonder having accurate chip placement capability is needed to ensure good solder joint formation. Conventional reflow method is still applicable for sizable solder bump of diameter being greater than 100 μm and larger than 150μm pitch [3]. The post underfill processes such as capillary underfill (CUF) and molded underfill (MUF) can be followed after the solder joints are formed. On the other hand, when the pitch of bumps and/or the thickness of the FC go down further, FC with copper pillar bumps bonded by TC process would be one of the solutions for fine-pitch FC applications. It has been shown that the bump pitch can be reduced to as small as 50 μm (inline pitch). This process also allows for better control on the solder squeezed out effect. However this process requires tight control on (i) the planarization between the FC and the bonding substrate and (ii) the stand-off of each solder joint. Good process parameters have to be established to ensure no solder collapse or open joint.

3D technology is envisioned to offer advanced integration capabilities, enabling heterogeneous system integration and offering improved performance and reduced power consumption thanks the so-called Through Silicon Vias (TSVs). Nevertheless, 3D integration is facing strong thermal issues due to its higher power density and reduced heat dissipation properties. In previous studies, it has been often reported the use of TSV insertion techniques for thermal mitigation in 3D stacked circuits. However, due to the thin oxide layer isolating TSVs from silicon substrate, the expected thermal mitigation is actually not effective for the current TSV technologies. This paper firstly provides an analytical study to project the potential benefits and drawbacks of using TSVs for thermal mitigation. Detailed FEM simulations and experimental silicon data from a dedicated thermal test chip are then used to confirm the projections and demonstrate that TSVs may even increase the temperature of hotspots. This paper secondly reports the study of the thermal performance of multiple TSV arrays using thermal simulations for various system-level configurations, including a WideIO compatible 3D circuit. Similar results are obtained where, besides not alleviating thermal issues, TSVs may produce exacerbated hotspots. The results presented in this paper indicate that the use of additional area costly TSVs for thermal mitigation is not worthy.