3D integrated system for advanced intelligent computing

Power delivery network (PDN) design is already a challenging problem for single die designs using advanced process technologies. For systems created using stacked dies with TSVs, several additional issues that affect power delivery and reliability have to be addressed. In stacked die configuration, the dies higher up in the stack-up experience additional drop and noise in their power supply as it propagates through the TSV networks of one or more dies placed lower in the stack-up. For the lower dies, the presence of the TSV farm and associated metals/vias affects the homogeneity of their own power delivery network. And if multiple dies share power and ground domains, then there could be an inter-die propagation of supply noise. So it becomes important that a PDN design and optimization flow for stacked die designs models and analyzes the presence of multiple dies and also the switching and the noise impact from the dies on each other. The analysis could be concurrent or model based, depending upon whether full databases for all the chips are available or their electrically equivalent models such as Chip Power Model (CPM) are available, respectively. For both of these approaches, a DC and time-domain analysis has to be done at the chip layout level to accurately predict the power/ground noise in the stacked die design. These analyses need to done starting early, in order to enable prototyping and design trade-off decisions. In this paper, a prototyping and verification solution for multi-die TSV based designs is outlined along with results from various design decisions undertaken.

With increasing core counts ushering in power-constrained 3-D multiprocessor system-on-chips (MPSoCs), optimizing communication power dissipated by the 3-D network-on-chip (NoC) fabric is critical. At the same time, with increased power densities in 3-D ICs, problems of IR drops in the power delivery network (PDN) as well as thermal hot spots on the 3-D die are becoming very severe. Even though the PDN and NoC design goals are nonoverlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider the design of the PDN, while designing NoCs. Moreover, for each new configuration of computation core and communication mapping on an MPSoC, the corresponding intercore communication patterns, 3-D on-chip thermal profile, as well as IR-drop distribution in the PDN can vary significantly. Based on this observation, we propose a novel design-time system-level application-specific cosynthesis framework that intelligently maps computation and communication resources on a die, for a given workload. The goal is to minimize the NoC power as well as chip-cooling power and optimize the 3-D PDN architecture; while meeting performance goals and satisfying thermal constraints, for a microfluidic cooling-based application-specific 3-D MPSoC. Our experimental results indicate that the proposed 3-D NoC-PDN cosynthesis framework is not only able to meet PDN design goals unlike prior 3-D NoC synthesis approaches, but also provides better overall optimality with the solution quality improvement of up to 35.4% over a probabilistic metaheuristic-based cooptimization approach proposed in prior work.

Power Delivery Network (PDN) is a critical component in modern System-on-Chip (SoC) designs. With the rapid development in applications, the quality of PDN, especially Package (PKG) PDN, determines whether a sufficient amount of power can be delivered to critical computing blocks. In conventional PKG design, PDN design typically takes multiple weeks including many manual iterations for optimization. Also, there is a large discrepancy between (i) quick simulation tools used for quick PDN quality assessment during the design phase, and (ii) the golden extraction tool used for signoff. This discrepancy may introduce more iterations. In this work, we propose a learning-based methodology to perform PKG PDN quality assessment both before layout (when only bump/ball maps, but no package routing, are available) and after layout (when routing is completed but no signoff analysis has been launched). Our contributions include (i) identification of important parameters to estimate the achievable PKG PDN quality in terms of bump inductance; (ii) the avoidance of unnecessary manual trial and error overheads in PKG PDN design; and (iii) more accurate design-phase PKG PDN quality assessment. We validate accuracy of our predictive models on PKG designs from industry. Experimental results show that, across a testbed of 17 industry PKG designs, we can predict bump inductance with an average absolute percentage error of 21.2% or less, given only pinmap and technology information. We improve prediction accuracy to achieve an average absolute percentage error of 17.5% or less when layout information is considered.

Suboptimal design of power delivery networks (PDNs) may cause performance deterioration and severe functional failures on high-speed computer platforms. Voltage regulators (VRs) distribute controlled voltage in the PDN to the active devices, providing a steady power supply at a desired DC voltage level with an acceptable noise level or ripple. Unacceptable voltage drops can be caused by transient switching currents at the devices. Many decoupling capacitors are commonly used to lower the PDN impedance profile in order to reduce power supply noise and to supply fast transient current to switching devices. However, commercially available decoupling capacitors typically present large manufacturing variability. In this article, we first propose an optimization methodology that gradually finds the best compensation parameter values of a buck converter VR to meet suitable stability criteria. Simultaneously, the number of parallel decoupling capacitors in the PDN is minimized while meeting a frequency-domain impedance profile specification and a time-domain minimum voltage droop requirement under nominal parameter values. Finally, a statistical analysis, yield estimation, and yield optimization of the nominally optimized PDN subject to large decoupling capacitor tolerances is presented. We consider the impedance profile, transient voltage droop, and VR stability as the responses of interest for yield calculation.

Three dimensional (3D) integration offers numerous electrical advantages like shorter interconnection distances between different dies in the stack, reduced signal delay, reduced interconnect power and design flexibilities. The main enabler of 3D integration is through-silicon-vias (TSVs) and stacking of multiple dies. Irrespective of these advantages, thermal management in 3D stacks poses significant challenges for the implementation of 3D integrated circuits. Even though extensive research work has been done in understanding the thermal management in two dimensional (2D) planar circuits for the past several decades, 3D integration offers a new set of challenges in terms of thermal management, which makes it difficult to readily apply the thermal management strategies available for 2D planar circuits. Over the past decade, some work has been done in thermal analysis and management of 3D stacks but still, knowledge is scattered and a comprehensive understanding is lacking. This research work focuses on bringing together the limited work on thermal analysis and thermal management in 3D vertically integrated circuits available in the literature. A compilation and analysis of the results from investigations on thermal management in 3D stacks is presented in this review with special emphasis on experimental studies conducted on different thermal management strategies. Furthermore, 3D integration technologies, thermal management challenges, and advanced 2D thermal management solutions are discussed.

Signal and power integrity are crucial for ensuring high performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) has become a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). In this paper, a new power delivery scheme is shown to significantly reduce switching noise at lower power. This concept has been demonstrated through theory, simulation, and measurements.

The rapid advancement of artificial intelligence (AI) has accelerated the semiconductor industry, driving chip performance requirements to unprecedented levels. However, conventional system-on-chip (SoC) designs are increasingly constrained by the physical and economic limits of monolithic scaling, where continued transistor miniaturization yields diminishing returns and rising fabrication costs. To address these challenges, the industry has shifted toward chiplet-based heterogeneous integration and advanced packaging technologies. By interconnecting multiple specialized chiplets through high-density, high-bandwidth interfaces, this modular approach improves scalability, reusability, and cost efficiency while enabling faster time-to-market. However, chiplet-based systems introduce significant design complexity, particularly in signal integrity (SI) and power integrity (PI), where highly constrained interconnects and power delivery networks must meet stringent electrical requirements. Traditional design methodologies rely heavily on expert-driven manual tuning and extensive full-wave electromagnetic simulations using electronic design automation (EDA) tools, resulting in long design cycles that can span weeks or months. To overcome these limitations, this thesis investigates the application of AI, particularly deep reinforcement learning (RL), to automate and optimize chiplet-based system design with a focus on SI and PI challenges in advanced packaging technologies. The research initially explores a supervised learning approach using convolutional neural networks (CNNs) to classify signal impairments from eye diagrams. While effective, this approach reveals a critical dependence on large labeled datasets, which are scarce in SI/PI domains, motivating a shift toward RL for autonomous design space exploration without labeled data. The first major contribution proposes an RL framework for automated power distribution network (PDN) design in a four-chiplet system. Two RL algorithms, Dueling Double Deep Q-Network (DDDQN) and Proximal Policy Optimization (PPO), are evaluated under different reward strategies. Results show that dense analytical rewards based on power domain squareness and bump proximity enable the RL agent to achieve lower self-impedance than human-designed PDNs, ensuring power integrity across 28 power domains. The complete PDN layout, which typically requires three months of manual effort, is generated in under one hour using a single GPU. The second contribution focuses on signal integrity optimization for chiplet interconnects in CoWoS redistribution layers (RDLs). An RL agent is trained using a reward function that balances eye width, voltage transfer function (VTF) crosstalk, and interconnect density. The agent explores design variations across data rates from 4 to 32 GT/s using a simulation environment integrated with commercial EDA tools. Experimental results demonstrate up to 24.67% improvement in eye width and over 22 dB reduction in VTF crosstalk while satisfying UCIe electrical specifications. The training process also generates labeled datasets for future supervised learning. The third contribution introduces an RL-based routing framework for UCIe bridge interconnects in advanced System-in-Package (SiP). Using Proximal Policy Optimization, the framework learns to generate routing layouts that comply with constraints such as ground-signal-ground structures, layer assignment, and congestion avoidance. It supports all UCIe module configurations and produces design rule check-compliant solutions within 100 training episodes, reducing design time from four weeks to less than one hour while improving signal distribution and reducing via usage. In summary, this thesis presents a unified AI-driven methodology for addressing SI and PI challenges in chiplet-based systems. The proposed RL frameworks significantly outperform traditional design approaches in both efficiency and quality, demonstrating the potential of deep RL to enable scalable and intelligent design automation for advanced packaging and chiplet-based architectures.

This paper introduces a process that allows customers to do IRDrop analysis on the package/SiP and PCB level. The component information such as the package model, power consumption and voltage regulator module (VRM) as well as power delivery network circuit can be used at the package and board level to perform static IRDrop analysis. The power consumption is used to obtain the current excitation while the VRM pins are used to provide the power supply. For the complicated package and PCB geometry structure, the progressive mesh scheme is used to extract the DC circuit model for their power delivery network. In order to meet the tolerance of current and voltage drop, the required VRM and IC components locations as well as stackup can be optimized according to the voltage drop in DC domain. The user can also view the voltage drop, current and temperature rise.

In this paper, a new concept of distributed port is proposed, and a systematic method for the modeling, analysis, and design of the high-speed power delivery network (PDN) is developed. The distributed port uses multiple lumped ports dispersed uniformly in the power-delivery networks to capture the distributed characteristics of the large and irregular power-delivery structures. This concept provides a feasible scheme for the accurate analysis of the whole or any part of a power-delivery network. The modeling methods and modeled results are discussed in depth. The applications of the distributed port in the PDN design, systematic PDN modeling, and package/connector performance evaluation and optimization are discussed in detail. The validity of the distributed port is demonstrated by numerical examples and verified by simulations and extractions.

In modern DRAM design, IR-drop has emerged as a critical factor leading to operation failures, primarily due to reduced metal resources and increased supply current demands. Consequently, estimating and addressing IR-drop throughout the DRAM design process has become a crucial sign-off consideration. The proposed comprehensive methodology for the power delivery network (PDN) includes accurate and efficient estimation at two key stages: early in the design process (Early PDN) and during post-physical design sign-off validation (Iterative PDN). The Early PDN approach employs simplified modeling to achieve reasonable accuracy, serving as a guideline for the initial PDN design. Subsequently, the Iterative PDN method provides a fast yet detailed analysis of the entire DRAM, including the PDN, ensuring it is suitable for final sign-off. By applying this methodology, PDN behavior can be effectively predicted and optimized, ensuring robustness. This enhances the reliability and performance of DRAM designs.

In this paper describes the four challenges in thermal management in communication devices. Four challenges in the electronic packaging industry are challenges in the cooling of three dimensional packages, challenges resulting from thermally induced warpages, thermal challenges arising from spreading and interface resistances and thermal challenges in the implementation of lead free solder. In three dimensional packaging technologies are now emerging field, in which tremendous reduction size and weight of wireless handheld devices. Thermally induced warpage become one of the major concerns in the automated manufacturing and assembly of multilayered PWBs. One of the big challenge in electronic packaging industry is to implement lead free solder alloy. Tin/silver/copper alloys are introduced as lead free solder in packaging.

This study examines the evolution, technical specifications, and future potential of submarine battery technologies, highlighting their role in advancing underwater operations. From lead-acid to modern lithium-ion and solid-state batteries, the chapter reviews how energy systems have transformed submarine capabilities in military, commercial, and scientific contexts. Key topics include battery design, safety risks, environmental impacts, and integration into operational frameworks. It explores advancements in energy density, efficiency, and sustainability while addressing challenges in thermal management, recycling, and cost. Emerging technologies such as fuel cells, lithium-sulfur batteries, and AI-supported systems are discussed, contributing to innovative and sustainable energy solutions for future submarine operations.

Aircraft thermal management: Practices, technology, system architectures, future challenges, and opportunities

Brief Historical Perspective in Thermal Management and the Shift Toward Management at the Nanoscale

The reliable Power Delivery Network (PDN) design is a challenging aspect in Three-Dimensional-Integrated-Circuits (3D-ICs). In order to ensure the robustness of the 3D PDN, the number and the locations of the Power/Ground (P/G) Through-Silicon-Vias (TSVs) should be carefully planned. Non-regular P/G TSV placement has superior performance compared to the regular one in terms of TSV count. However, the corresponding deadspace optimization is necessary, which complicates the traditional 3D floorplanning. In this work, we propose an efficient deadspace-aware P/G TSV planning combined with the 3D floorplanning to simultaneously place the 2D blocks and P/G TSVs to minimize the total wirelength and the number of inserted TSVs under IR-drop and fixed-outline constraints.