Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN

With increasing core counts ushering in power-constrained 3-D multiprocessor system-on-chips (MPSoCs), optimizing communication power dissipated by the 3-D network-on-chip (NoC) fabric is critical. At the same time, with increased power densities in 3-D ICs, problems of IR drops in the power delivery network (PDN) as well as thermal hot spots on the 3-D die are becoming very severe. Even though the PDN and NoC design goals are nonoverlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider the design of the PDN, while designing NoCs. Moreover, for each new configuration of computation core and communication mapping on an MPSoC, the corresponding intercore communication patterns, 3-D on-chip thermal profile, as well as IR-drop distribution in the PDN can vary significantly. Based on this observation, we propose a novel design-time system-level application-specific cosynthesis framework that intelligently maps computation and communication resources on a die, for a given workload. The goal is to minimize the NoC power as well as chip-cooling power and optimize the 3-D PDN architecture; while meeting performance goals and satisfying thermal constraints, for a microfluidic cooling-based application-specific 3-D MPSoC. Our experimental results indicate that the proposed 3-D NoC-PDN cosynthesis framework is not only able to meet PDN design goals unlike prior 3-D NoC synthesis approaches, but also provides better overall optimality with the solution quality improvement of up to 35.4% over a probabilistic metaheuristic-based cooptimization approach proposed in prior work.

Power Delivery Network (PDN) is a critical component in modern System-on-Chip (SoC) designs. With the rapid development in applications, the quality of PDN, especially Package (PKG) PDN, determines whether a sufficient amount of power can be delivered to critical computing blocks. In conventional PKG design, PDN design typically takes multiple weeks including many manual iterations for optimization. Also, there is a large discrepancy between (i) quick simulation tools used for quick PDN quality assessment during the design phase, and (ii) the golden extraction tool used for signoff. This discrepancy may introduce more iterations. In this work, we propose a learning-based methodology to perform PKG PDN quality assessment both before layout (when only bump/ball maps, but no package routing, are available) and after layout (when routing is completed but no signoff analysis has been launched). Our contributions include (i) identification of important parameters to estimate the achievable PKG PDN quality in terms of bump inductance; (ii) the avoidance of unnecessary manual trial and error overheads in PKG PDN design; and (iii) more accurate design-phase PKG PDN quality assessment. We validate accuracy of our predictive models on PKG designs from industry. Experimental results show that, across a testbed of 17 industry PKG designs, we can predict bump inductance with an average absolute percentage error of 21.2% or less, given only pinmap and technology information. We improve prediction accuracy to achieve an average absolute percentage error of 17.5% or less when layout information is considered.

Suboptimal design of power delivery networks (PDNs) may cause performance deterioration and severe functional failures on high-speed computer platforms. Voltage regulators (VRs) distribute controlled voltage in the PDN to the active devices, providing a steady power supply at a desired DC voltage level with an acceptable noise level or ripple. Unacceptable voltage drops can be caused by transient switching currents at the devices. Many decoupling capacitors are commonly used to lower the PDN impedance profile in order to reduce power supply noise and to supply fast transient current to switching devices. However, commercially available decoupling capacitors typically present large manufacturing variability. In this article, we first propose an optimization methodology that gradually finds the best compensation parameter values of a buck converter VR to meet suitable stability criteria. Simultaneously, the number of parallel decoupling capacitors in the PDN is minimized while meeting a frequency-domain impedance profile specification and a time-domain minimum voltage droop requirement under nominal parameter values. Finally, a statistical analysis, yield estimation, and yield optimization of the nominally optimized PDN subject to large decoupling capacitor tolerances is presented. We consider the impedance profile, transient voltage droop, and VR stability as the responses of interest for yield calculation.

In this paper, an analysis of filtering window impacts on estimation accuracy of electromagnetic (EM) information leakage from exposed areas in power delivery network (PDN) of cryptographic devices is presented. There are exposed areas in the PDN such as decoupling capacitors, through via plating, and small power/ground interconnections where full-byte secret key information can be leaked in the form of EM fields. Various waveforms are measured using EM field probes on the PDN of the target cryptographic device. Correlation electromagnetic analysis (CEMA), field distribution analysis, and secret key extraction are conducted based on the measured waveforms via EM field radiation from the exposed PDN. It is verified that adopting a proper filtering window to remove impacts of noise irrelevant to secret key processing is important for an accurate and efficient estimation of the information leakage from the PDN. Based on the experiment and analysis results, an efficient leakage location detection method using the filtered waveforms is discussed.

Power delivery network (PDN) design is already a challenging problem for single die designs using advanced process technologies. For systems created using stacked dies with TSVs, several additional issues that affect power delivery and reliability have to be addressed. In stacked die configuration, the dies higher up in the stack-up experience additional drop and noise in their power supply as it propagates through the TSV networks of one or more dies placed lower in the stack-up. For the lower dies, the presence of the TSV farm and associated metals/vias affects the homogeneity of their own power delivery network. And if multiple dies share power and ground domains, then there could be an inter-die propagation of supply noise. So it becomes important that a PDN design and optimization flow for stacked die designs models and analyzes the presence of multiple dies and also the switching and the noise impact from the dies on each other. The analysis could be concurrent or model based, depending upon whether full databases for all the chips are available or their electrically equivalent models such as Chip Power Model (CPM) are available, respectively. For both of these approaches, a DC and time-domain analysis has to be done at the chip layout level to accurately predict the power/ground noise in the stacked die design. These analyses need to done starting early, in order to enable prototyping and design trade-off decisions. In this paper, a prototyping and verification solution for multi-die TSV based designs is outlined along with results from various design decisions undertaken.

High-performance microprocessors and accelerators, integral to data centers, require power delivery networks capable of managing higher currents and power densities while operating at lower voltages. The surge in generative AI applications is reshaping the landscape of semiconductor hardware, necessitating advanced power delivery solutions to meet escalating demands for efficiency and performance. As AI workloads intensify, traditional power delivery methods struggle to provide the necessary energy without compromising spatial constraints on circuit boards. This paper addresses the critical challenges posed by embedded passive components, specifically capacitors and inductors, while demonstrating an embedded voltage regulation (eVR) STile™. We introduce an innovative approach that leverages embedded passive technology to enhance power efficiency. This paper will demonstrate the integration of capacitors and inductors directly into the package substrate to enable for the first time and subsequently vertical power delivery directly into the package substrate. This demonstration of highly integrated passive components serves to optimize the power delivery network through reduction in the power path length as well as leveraging high performance passive components. By addressing these power delivery challenges, we pave the way for the next generation of semiconductor hardware tailored to the demands of next generation AI applications. Ensuring optimal power signal integrity is vital for maintaining stable voltage delivery across a wide frequency range. A standard design methodology focuses on minimizing the impedance seen by the load’s input nodes, thereby reducing voltage ripple and droop during transient events. STile technology improves performance by embedding high capacitance density capacitors close to the load and combining them with complimentary inductors to, significantly reduce parasitics and optimize space for both VPD and embedded voltage regulation (eVR) solutions. This paper will demonstrate the ability to integrate these passive components specifically designed to support integrated voltage regulation inside of the package. This paper will show configurations of passive components that support a variety of different domains for traditional high performance computing die. This paper will also demonstrate the superior performance capable of being achieved as compared to traditional power delivery network’s. These traditional power delivery networks perform the voltage conversion from 48V to POL (Point of Load) voltages in discrete and bulky modules on the periphery of the printed circuit board. These modules combine the use of inductors, capacitors and actives however, are significantly far away from the load that efficiency of the network becomes a problem. To minimize I²R losses, efficient power delivery demands higher voltages and low current levels at the package substrate level. While conventional power regulator topologies typically utilize inductors to achieve high conversion efficiencies, integrating inductors onto the die can complicate design and elevate costs. The STile technology provides a groundbreaking solution by enabling the co-location of inductors and capacitors within a customizable three-terminal LC passive module (patent pending) embedded in the core substrate. This integration allows for precise alignment with processor power domains, significantly reducing the need for lateral metal routing. Additionally, the flexible layout of the LC passive modules supports multiple power domains, facilitating interleaved multiphase outputs and innovative configurations such as sharing output capacitors among several inductors. By addressing these design challenges, eVR STile technology significantly enhances power delivery efficiency while meeting the stringent demands of next-generation semiconductor applications. This paper emphasizes the development of advanced, highly integrated capacitor and inductor solutions that deliver superior performance for next-generation power delivery systems. By leveraging STile technology, we illustrate how embedding capacitors and inductors within the substrate not only enhances power signal integrity and minimizes parasitics but also optimizes space for embedded voltage regulation (eVR). This innovative platform enables the creation of custom eVR designs tailored to specific application requirements, significantly improving efficiency in high-performance computing environments. Through our findings, we highlight the transformative potential of these embedded passive components in addressing the power delivery challenges faced by next generation artificial intelligence chips.

This paper describes effect of designing resonant free power delivery network (PDN) on the performance of voltage regulator modules (VRM) commonly used in microprocessor systems. The performance parameters of the VRM as a result of decoupling capacitors (DECAPS) added at different stages of the PDN to realize the resonant free target impedance is described using the output impedance as a key parameter. Parametric curves and simulation results are presented to support the validity of the design oriented analysis with special emphasis on the performance of the VRM considering voltage sensing for feedback at different stages of the microprocessor PDN

This paper introduces a process that allows customers to do IRDrop analysis on the package/SiP and PCB level. The component information such as the package model, power consumption and voltage regulator module (VRM) as well as power delivery network circuit can be used at the package and board level to perform static IRDrop analysis. The power consumption is used to obtain the current excitation while the VRM pins are used to provide the power supply. For the complicated package and PCB geometry structure, the progressive mesh scheme is used to extract the DC circuit model for their power delivery network. In order to meet the tolerance of current and voltage drop, the required VRM and IC components locations as well as stackup can be optimized according to the voltage drop in DC domain. The user can also view the voltage drop, current and temperature rise.

In this paper, a new concept of distributed port is proposed, and a systematic method for the modeling, analysis, and design of the high-speed power delivery network (PDN) is developed. The distributed port uses multiple lumped ports dispersed uniformly in the power-delivery networks to capture the distributed characteristics of the large and irregular power-delivery structures. This concept provides a feasible scheme for the accurate analysis of the whole or any part of a power-delivery network. The modeling methods and modeled results are discussed in depth. The applications of the distributed port in the PDN design, systematic PDN modeling, and package/connector performance evaluation and optimization are discussed in detail. The validity of the distributed port is demonstrated by numerical examples and verified by simulations and extractions.

As the complexity increases, power delivery network (PDN) optimization becomes a more important step in a modern design. In order to construct a robust PDN, most classic PDN optimization methods focus on adjusting the dimensions of power stripes. However, this approach becomes infeasible when voltage violation regions also have severe routing congestion. Hence, this paper proposes a delicate procedure to insert additional power stripes to reduce voltage violation while maintaining routability. In the beginning, IR-drop high related regions are identified to reveal those locations which are thirsty for more currents. Then, we solve a minimum-cost flow problem to find the topologies of power delivery paths (PDPs) from power sources to these regions and determine the widths of edges in each PDP so that enough currents can be provided to these regions. Moreover, vertical power stripes (VPSs for short) are inserted to the locations which have less routing congestion and severe voltage violations by the dynamic programming to reduce a probability to deteriorate routability. Finally, more wires will be inserted to IR-drop high related regions if there still exist voltage violations. Experimental results show that our method can use much less routing resource and induce less routing congestion to meet IR-drop constraint in industry designs.

The reliable Power Delivery Network (PDN) design is a challenging aspect in Three-Dimensional-Integrated-Circuits (3D-ICs). In order to ensure the robustness of the 3D PDN, the number and the locations of the Power/Ground (P/G) Through-Silicon-Vias (TSVs) should be carefully planned. Non-regular P/G TSV placement has superior performance compared to the regular one in terms of TSV count. However, the corresponding deadspace optimization is necessary, which complicates the traditional 3D floorplanning. In this work, we propose an efficient deadspace-aware P/G TSV planning combined with the 3D floorplanning to simultaneously place the 2D blocks and P/G TSVs to minimize the total wirelength and the number of inserted TSVs under IR-drop and fixed-outline constraints.

With the trend toward higher operating frequencies, the simultaneous switching noise (SSN) problem is being aggravated. The required noise tolerance for testing scenarios is more demanding so that it raises the importance of control over SSN in the interface board between a device under test and an automatic test equipment. Low noise is especially important when testing mixed-signal devices, in which noisy digital circuits and noise-sensitive analog circuits share a power delivery network (PDN). To prevent noise coupling between circuits and provide low-noise testing environment, the method of supplying power through transmission lines instead of a voltage plane can be employed. The power transmission line (PTL) not only provides isolation between circuits, but also removes the voltage plane along with its adverse effects such as the cavity resonance and the return path discontinuity. In this paper, the first demonstration of a Constant Current Power Transmission Line (CCPTL)-based single-ended signaling scheme is presented. The measurement results show that the CCPTL-based PDN improves the eye quality at the receiver side as compared to the power-plane-based PDN.

Power delivery network (PDN) is a distributed RLC network with its dominant resonance frequency in the low-to-middle frequency range. Though high-performance chips' working frequencies are much higher than this resonance frequency in general, chip runtime loading frequency is not. When a chip executes a chunk of instructions repeatedly, the induced current load may have harmonic components close to this resonance frequency, causing excessive power integrity degradation. Existing PDN design solutions are, however, mainly targeted at reducing high-frequency noise and not effective to suppress such resonance noise. In this work, we propose a novel approach to proactively suppress this type of noise. A method based on a high dimension generalized Markov process is developed to predict current load variation. Based on such prediction, a clock frequency actuator design is proposed to proactively select an optimal clock frequency to suppress the resonance. To the best of our knowledge, this is the first in-depth study on proactively reducing runtime instruction execution induced PDN resonance noise.

Power supply induced clock jitter accumulation is a function of several variables including the power supply rejection characteristics of circuits in the signal path, signal path electrical length, signaling frequency, and voltage supply noise magnitude and frequency. Brute force, closed-loop, transistor-level modeling and simulation of clock timing in the presence of an extracted power delivery network are resource intensive. In addition, circuit and power delivery network designs are often not complete enough to run such analyses at an early stage in the design cycle, and the longer a design waits to identify circuit and supply sensitivities, the more costly the corrections become. Understanding the relationships between the signal path electrical length, signaling frequency and supply noise frequency enables early jitter estimation and can be used to drive both circuit and power delivery network design optimization. This paper summarizes the general inter-dependencies between these variables and then demonstrates how these principles might be used to make design optimizations in the context of the Low Power Double Data Rate Four (LPDDR4) interface.

With each technology generation, delivering a timevarying current with reduced nominal supply voltage variation is becoming more difficult due to increasing current and power requirements. The power delivery network design becomes much more complex and requires accurate analysis and optimizations at all levels of abstraction in order to meet the specifications. In this paper, we describe techniques for estimation of the supply voltage variations that can be used in the design of the power delivery network. We also describe the decoupling capacitor hierarchy that provides a low impedance to the increasing high-frequency current demand and limits the supply voltage variations. Techniques for high-level power estimation that can be used for performance vs. power trade-offs to reduce the current and power requirements of the circuit are also presented.