Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery Network

High-performance microprocessors and accelerators, integral to data centers, require power delivery networks capable of managing higher currents and power densities while operating at lower voltages. The surge in generative AI applications is reshaping the landscape of semiconductor hardware, necessitating advanced power delivery solutions to meet escalating demands for efficiency and performance. As AI workloads intensify, traditional power delivery methods struggle to provide the necessary energy without compromising spatial constraints on circuit boards. This paper addresses the critical challenges posed by embedded passive components, specifically capacitors and inductors, while demonstrating an embedded voltage regulation (eVR) STile™. We introduce an innovative approach that leverages embedded passive technology to enhance power efficiency. This paper will demonstrate the integration of capacitors and inductors directly into the package substrate to enable for the first time and subsequently vertical power delivery directly into the package substrate. This demonstration of highly integrated passive components serves to optimize the power delivery network through reduction in the power path length as well as leveraging high performance passive components. By addressing these power delivery challenges, we pave the way for the next generation of semiconductor hardware tailored to the demands of next generation AI applications. Ensuring optimal power signal integrity is vital for maintaining stable voltage delivery across a wide frequency range. A standard design methodology focuses on minimizing the impedance seen by the load’s input nodes, thereby reducing voltage ripple and droop during transient events. STile technology improves performance by embedding high capacitance density capacitors close to the load and combining them with complimentary inductors to, significantly reduce parasitics and optimize space for both VPD and embedded voltage regulation (eVR) solutions. This paper will demonstrate the ability to integrate these passive components specifically designed to support integrated voltage regulation inside of the package. This paper will show configurations of passive components that support a variety of different domains for traditional high performance computing die. This paper will also demonstrate the superior performance capable of being achieved as compared to traditional power delivery network’s. These traditional power delivery networks perform the voltage conversion from 48V to POL (Point of Load) voltages in discrete and bulky modules on the periphery of the printed circuit board. These modules combine the use of inductors, capacitors and actives however, are significantly far away from the load that efficiency of the network becomes a problem. To minimize I²R losses, efficient power delivery demands higher voltages and low current levels at the package substrate level. While conventional power regulator topologies typically utilize inductors to achieve high conversion efficiencies, integrating inductors onto the die can complicate design and elevate costs. The STile technology provides a groundbreaking solution by enabling the co-location of inductors and capacitors within a customizable three-terminal LC passive module (patent pending) embedded in the core substrate. This integration allows for precise alignment with processor power domains, significantly reducing the need for lateral metal routing. Additionally, the flexible layout of the LC passive modules supports multiple power domains, facilitating interleaved multiphase outputs and innovative configurations such as sharing output capacitors among several inductors. By addressing these design challenges, eVR STile technology significantly enhances power delivery efficiency while meeting the stringent demands of next-generation semiconductor applications. This paper emphasizes the development of advanced, highly integrated capacitor and inductor solutions that deliver superior performance for next-generation power delivery systems. By leveraging STile technology, we illustrate how embedding capacitors and inductors within the substrate not only enhances power signal integrity and minimizes parasitics but also optimizes space for embedded voltage regulation (eVR). This innovative platform enables the creation of custom eVR designs tailored to specific application requirements, significantly improving efficiency in high-performance computing environments. Through our findings, we highlight the transformative potential of these embedded passive components in addressing the power delivery challenges faced by next generation artificial intelligence chips.

In modern DRAM design, IR-drop has emerged as a critical factor leading to operation failures, primarily due to reduced metal resources and increased supply current demands. Consequently, estimating and addressing IR-drop throughout the DRAM design process has become a crucial sign-off consideration. The proposed comprehensive methodology for the power delivery network (PDN) includes accurate and efficient estimation at two key stages: early in the design process (Early PDN) and during post-physical design sign-off validation (Iterative PDN). The Early PDN approach employs simplified modeling to achieve reasonable accuracy, serving as a guideline for the initial PDN design. Subsequently, the Iterative PDN method provides a fast yet detailed analysis of the entire DRAM, including the PDN, ensuring it is suitable for final sign-off. By applying this methodology, PDN behavior can be effectively predicted and optimized, ensuring robustness. This enhances the reliability and performance of DRAM designs.

Fast and accurate pre-routing timing prediction is essential in the chip design flow. However, existing machine learning (ML)assisted pre-routing timing methods often overlook the impact of power delivery networks (PDNs), which contribute to IR drop and routing congestion. This limitation can make these methods less practical for realworld circuit design flows. To address this, we propose two specialized encoders-an IR drop-aware encoder and a routing congestion-aware encoder-that effectively capture PDN effects through multimodal fusion of netlist, layout, and PDN data. To mitigate the challenges of imbalanced multimodal fusion, we further develop a Pareto optimization approach to ensure balanced utilization of all modalities, enhancing timing prediction accuracy. Comprehensive experiments on large-scale open-source designs using TSMC’s 16 nm technology node validate the superiority of our model over state-of-the-art pre-routing timing prediction methods.

Modern client processors typically use one of three commonly-used power delivery network (PDN) architectures: 1) motherboard voltage regulators (MBVR), 2) integrated voltage regulators (IVR), and 3) low dropout voltage regulators (LDO). We observe that the energy-efficiency of each of these PDNs varies with the processor power (e.g, thermal design power (TDP) and dynamic power-state) and workload characteristics (e.g., work-load type and computational intensity). This leads to energy-inefficiency and performance loss, as modern client processors operate across a wide spectrum of power consumption and execute a wide variety of workloads. To address this inefficiency, we propose FlexWatts, a hybrid adaptive PDN for modern client processors whose goal is to provide high energy-efficiency across the processor's wide range of power consumption and workloads. FlexWatts provides high energy-efficiency by intelligently and dynamically allocating PDNs to processor domains depending on the processor's power consumption and workload. FlexWatts is based on three key ideas. First, FlexWatts combines IVRs and LDOs in a novel way to share multiple on-chip and off-chip resources and thus reduce cost, as well as board and die area overheads. This hybrid PDN is allocated for processor domains with a wide power consumption range (e.g., CPU cores and graphics engines) and it dynamically switches between two modes: IVR-Mode and LDO-Mode, depending on the power consumption. Second, for all other processor domains (that have a low and narrow power range, e.g., the IO domain), FlexWatts statically allocates off-chip VRs, which have high energy-efficiency for low and narrow power ranges. Third, FlexWatts introduces a novel prediction algorithm that automatically switches the hybrid PDN to the mode (IVR-Mode or LDO-Mode) that is the most beneficial based on processor power consumption and workload characteristics. To evaluate the tradeoffs of PDNs, we develop and open-source PDNspot, the first validated architectural PDN model that enables quantitative analysis of PDN metrics. Using PDNspot, we evaluate FlexWatts on a wide variety of SPEC CPU2006, graphics (3DMark06), and battery life (e.g., video playback) workloads against IVR, the state-of-the-art PDN in modern client processors. For a 4 W thermal design power (TDP) processor, FlexWatts improves the average performance of the SPEC CPU2006 and 3DMark06 workloads by 22% and 25%, respectively. For battery life workloads, FlexWatts reduces the average power consumption of video playback by 11% across all tested TDPs (4W-50W). FlexWatts has comparable cost and area overhead to IVR. We conclude that FlexWatts provides high energy-efficiency across a modern client processor's wide range of power consumption and wide variety of workloads, with minimal overhead.

Placing multiple voltage regulators onto the die is an effective way of enabling distributed on-chip voltage regulation and provides significant benefits in suppressing various types of power supply noise. However, the complex interactions between the active voltage regulators and the large passive subnetwork may render the complete power delivery network (PDN) unstable, leading to design failures. While traditional stability measures such as phase margin are not applicable to regulated PDNs that have a large number of loops, a brute-force analysis of network stability can be impractical due to the high complexity of a given PDN. We present a hybrid stability margin concept and the associated stability-checking method for PDNs with integrated linear low-dropout voltage regulators (LDOs). With theoretical rigor, the proposed approach is local in the sense that the stability of the entire network can be efficiently examined through a hybrid stability constraint that is defined locally for individual LDOs. In the same spirit, we propose a localized LDO design methodology that optimizes individual LDOs in a stand-alone manner while ensuring the network-level stability. Key circuit-level design considerations and tradeoffs involved in stability-ensuring LDO design are also discussed.

In-place diagnosis of off-chip power delivery resonance is demonstrated with on-chip waveform capturer and power delivery network (PDN) exciter that were prototyped in a 65 nm CMOS technology. Oscillatory waveforms are captured after the excitation of PDN, from which an LCR lumped equivalent circuit of PDN seen by on-chip circuits is algorithmically derived. The consistency of component values is confirmed among the demonstrated in-place diagnosis and full-wave analysis.

Power integrity design has been a challenging task especially with devices that high in power consumption but require high performance and with very tight voltage budgeting. Most of the time, the solution space is also limited by the product cost target. Designer will need to validate the power delivery network (PDN) performance with various design operation activities to identify the worst-case current profile. Step load current is one of the common profiles that is used to verify the PDN dynamic noise against the voltage specification. This paper introduces a formulation to estimate the PDN transient response to the step load current profile and the induced 1st droop voltage noise. It provides a quantitative model to analyze the PDN characteristic and its response with different step load bandwidth profile. PDN bandwidth metric is also introduced in the formulation to study the relationship with the step load bandwidth. The PDN step load response will be separated to resistive and reactive impedance response and as well the ripple from the LC oscillation. This serves as the dynamic voltage budgeting methodology with respect to 1st droop event to quantify the IR drop and ripple voltage noise budget across board, package and die to meet the product voltage specification.

With increasing core counts ushering in power-constrained 3-D multiprocessor system-on-chips (MPSoCs), optimizing communication power dissipated by the 3-D network-on-chip (NoC) fabric is critical. At the same time, with increased power densities in 3-D ICs, problems of IR drops in the power delivery network (PDN) as well as thermal hot spots on the 3-D die are becoming very severe. Even though the PDN and NoC design goals are nonoverlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider the design of the PDN, while designing NoCs. Moreover, for each new configuration of computation core and communication mapping on an MPSoC, the corresponding intercore communication patterns, 3-D on-chip thermal profile, as well as IR-drop distribution in the PDN can vary significantly. Based on this observation, we propose a novel design-time system-level application-specific cosynthesis framework that intelligently maps computation and communication resources on a die, for a given workload. The goal is to minimize the NoC power as well as chip-cooling power and optimize the 3-D PDN architecture; while meeting performance goals and satisfying thermal constraints, for a microfluidic cooling-based application-specific 3-D MPSoC. Our experimental results indicate that the proposed 3-D NoC-PDN cosynthesis framework is not only able to meet PDN design goals unlike prior 3-D NoC synthesis approaches, but also provides better overall optimality with the solution quality improvement of up to 35.4% over a probabilistic metaheuristic-based cooptimization approach proposed in prior work.

In this work, we propose an analytical approach for accurate estimation on on-die decoupling capacitance in the power delivery network (PDN) of an integrated chip (IC). This paper suggests a simplified model of PDN which avoids the complex mesh structures traditionally generated but still provides a good fit model with measurement. The suggested model consists of branched multiple cells in a chained node formation. By manipulating multiple variables accounting for a complex PDN structure, the curve fitting process was performed and the best-fitted curve was found to be valid with less than 3% error tolerance through the solution-search processes by comparing capacitor values in a known mesh structure. Consequently, complex matrix PDN can be simplified and converted to an analytical model through the proposed chained structure. This approach is expected to effectively validate the value of implemented decoupling capacitance in the PDN of a designed IC with conventional low-impedance measurement techniques.

Power Delivery Network (PDN) is a critical component in modern System-on-Chip (SoC) designs. With the rapid development in applications, the quality of PDN, especially Package (PKG) PDN, determines whether a sufficient amount of power can be delivered to critical computing blocks. In conventional PKG design, PDN design typically takes multiple weeks including many manual iterations for optimization. Also, there is a large discrepancy between (i) quick simulation tools used for quick PDN quality assessment during the design phase, and (ii) the golden extraction tool used for signoff. This discrepancy may introduce more iterations. In this work, we propose a learning-based methodology to perform PKG PDN quality assessment both before layout (when only bump/ball maps, but no package routing, are available) and after layout (when routing is completed but no signoff analysis has been launched). Our contributions include (i) identification of important parameters to estimate the achievable PKG PDN quality in terms of bump inductance; (ii) the avoidance of unnecessary manual trial and error overheads in PKG PDN design; and (iii) more accurate design-phase PKG PDN quality assessment. We validate accuracy of our predictive models on PKG designs from industry. Experimental results show that, across a testbed of 17 industry PKG designs, we can predict bump inductance with an average absolute percentage error of 21.2% or less, given only pinmap and technology information. We improve prediction accuracy to achieve an average absolute percentage error of 17.5% or less when layout information is considered.

Power delivery network (PDN) design is already a challenging problem for single die designs using advanced process technologies. For systems created using stacked dies with TSVs, several additional issues that affect power delivery and reliability have to be addressed. In stacked die configuration, the dies higher up in the stack-up experience additional drop and noise in their power supply as it propagates through the TSV networks of one or more dies placed lower in the stack-up. For the lower dies, the presence of the TSV farm and associated metals/vias affects the homogeneity of their own power delivery network. And if multiple dies share power and ground domains, then there could be an inter-die propagation of supply noise. So it becomes important that a PDN design and optimization flow for stacked die designs models and analyzes the presence of multiple dies and also the switching and the noise impact from the dies on each other. The analysis could be concurrent or model based, depending upon whether full databases for all the chips are available or their electrically equivalent models such as Chip Power Model (CPM) are available, respectively. For both of these approaches, a DC and time-domain analysis has to be done at the chip layout level to accurately predict the power/ground noise in the stacked die design. These analyses need to done starting early, in order to enable prototyping and design trade-off decisions. In this paper, a prototyping and verification solution for multi-die TSV based designs is outlined along with results from various design decisions undertaken.

In this paper, a new concept of distributed port is proposed, and a systematic method for the modeling, analysis, and design of the high-speed power delivery network (PDN) is developed. The distributed port uses multiple lumped ports dispersed uniformly in the power-delivery networks to capture the distributed characteristics of the large and irregular power-delivery structures. This concept provides a feasible scheme for the accurate analysis of the whole or any part of a power-delivery network. The modeling methods and modeled results are discussed in depth. The applications of the distributed port in the PDN design, systematic PDN modeling, and package/connector performance evaluation and optimization are discussed in detail. The validity of the distributed port is demonstrated by numerical examples and verified by simulations and extractions.

Suboptimal design of power delivery networks (PDNs) may cause performance deterioration and severe functional failures on high-speed computer platforms. Voltage regulators (VRs) distribute controlled voltage in the PDN to the active devices, providing a steady power supply at a desired DC voltage level with an acceptable noise level or ripple. Unacceptable voltage drops can be caused by transient switching currents at the devices. Many decoupling capacitors are commonly used to lower the PDN impedance profile in order to reduce power supply noise and to supply fast transient current to switching devices. However, commercially available decoupling capacitors typically present large manufacturing variability. In this article, we first propose an optimization methodology that gradually finds the best compensation parameter values of a buck converter VR to meet suitable stability criteria. Simultaneously, the number of parallel decoupling capacitors in the PDN is minimized while meeting a frequency-domain impedance profile specification and a time-domain minimum voltage droop requirement under nominal parameter values. Finally, a statistical analysis, yield estimation, and yield optimization of the nominally optimized PDN subject to large decoupling capacitor tolerances is presented. We consider the impedance profile, transient voltage droop, and VR stability as the responses of interest for yield calculation.

In this paper, an analysis of filtering window impacts on estimation accuracy of electromagnetic (EM) information leakage from exposed areas in power delivery network (PDN) of cryptographic devices is presented. There are exposed areas in the PDN such as decoupling capacitors, through via plating, and small power/ground interconnections where full-byte secret key information can be leaked in the form of EM fields. Various waveforms are measured using EM field probes on the PDN of the target cryptographic device. Correlation electromagnetic analysis (CEMA), field distribution analysis, and secret key extraction are conducted based on the measured waveforms via EM field radiation from the exposed PDN. It is verified that adopting a proper filtering window to remove impacts of noise irrelevant to secret key processing is important for an accurate and efficient estimation of the information leakage from the PDN. Based on the experiment and analysis results, an efficient leakage location detection method using the filtered waveforms is discussed.

In this paper, we conduct analysis of the power delivery network (PDN) induced crosstalk impacts on the high-speed signaling in ultra-thin and high permittivity substrates. When the PDN impedance is high, the return current discontinuity occurs in signal via transition and causes noise through power/ground planes. Therefore, to reduce the PDN impedance, although the decoupling capacitors are used in printed circuit board (PCB) design, the effective bandwidth and design space have limits. Meanwhile, the ultra-thin and high permittivity substrate has capability of reducing the PDN impedance in the wideband. Using electromagnetic (EM) and circuit simulations, we compared the crosstalk impacts by analyzing the insertion loss, PDN impedance, and eye diagram in three substrates. The eye diagrams were simulated under the situation that the clock signal with data rate (DR) that corresponds to the frequency of (1,0) mode of PDN on an aggressor, which is ten times line width away from a victim. We compared the eye-opening voltage and power/ground noise amount among with/without aggressor and each DR of victim. As a result, we found that the ultra-thin and high permittivity substrate can significantly suppress the PDN induced crosstalk impacts compared to the conventional flame-retardant type 4 (FR-4) substrate. In addition, because the PDN impedance is reduced in the wideband, these substrates can provide a good return path for signal vias in any position mounted on the PCBs and are helpful for various issues related to the PDN impedance.