3D-TSV vertical interconnection method using Cu/SnAg double bumps

3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.

In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through Si via connections were formed by UV laser drilling technology. Laser drilling is a non-contact manufacture method and laser beam with high energy can be focused to a small spot (15 mum beam diameter) for material ablating and removing without mask used. Several processes are the keys to accomplish 3D stacking, such as wafer thinning process, through silicon via forming process, dielectric layer forming process, metallization process, and inter chips bonding process. By integration of the mentioned key processes, a 3D chip stacking structure with 10 layers was carried out. The thickness of chip was 100 mum. Daisy chain pattern was designed for the electrical measurement of 3D stacking structure. The testing results show that the resistance of multi- chip stacking structure is about 0.056 Omega/cm. Some reliability test, such as temperature cycling test and pressure cooker test were also done. These testing results verified this PCB processing compatible 3D chip stacking technology with low cost is a reliable structure for 3D SiP (System in Packaging) module application.

With the increased demand of functionality in electronic device, three dimensional integration circuits technology together with downscaling of interconnection pitch present an important role for the development of next generation electronics. In the current types of interconnects, solder micro bumps have received much attention due to its low cost in material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the UBM structure/material will show a significant influence on the reliability performances of the solder micro bump joints. However, which UBM structure/material for fine pitch solder micro bump joint presents the better reliability properties is not concluded yet until now. In this study, the effect of UBM structural/material on the reliability properties of lead-free solder micro interconnections with a pitch of 30μm was discussed. The chip-on-chip test vehicle with solder micro bump interconnections having a diameter of 18 μm was adopted to evaluate the effects of UBM structure/material. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. In this study, three types of UBM were selected on the silicon carrier: they were single copper layer with a thickness of 8μm; the Cu/Ni layer with the thickness of 5μm/3μm and the Cu/Ni/Au layer with the thickness of 5μm/3μm/0.5μm. The UBM was electro-plated on the Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. For the silicon carrier with the bump structure of Cu/Sn and Cu/Ni/Sn, the silicon test chip with solder micro bump of Cu/Sn was used for chip bonding. The test chip having the solder micro bump of Cu/Sn and Cu//Ni/Sn was used for bonding with the silicon carrier having the Cu/Ni/Au UBM. In chip stacking process, we adopted the fluxless thermocompression process for each type of micro joints. After chip bonding process, the fine gap between bonded chips was filled by capillary type of underfill. The influence of underfill on the reliability of solder micro bump interconnects with various combinations of UBM structures were estimated also. After the assembly process, temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were performed on the chip-stacking module to assess the effect of UBM structure/material on the reliability of solder micro bump interconnections. The results of reliability test revealed that only Cu/Sn/Au/Ni/Cu micro joint could not pass the TCT and HTS of 1000 cycles. After reliability test, the Cu/Sn/Cu joints showed the evidently microstructural evolution while the Cu/Ni/Sn/Cu joints did not show apparent microstructure change among all the types of micro joints and still revealed the most contents of residual solder within the joint. On the other hand, the existence of Au layer upon the UBM caused the complicated interface reaction between solder and UBM, which presented a negative effect during long-term reliability performance. The reliability results also displayed that the introduction of underfill could apparently enhance the reliability of micro joint under mechanical evaluation. From the results of EM reliability test, all the types of the micro joints showed excellent electromigration resistance under current stress of 0.08A at an ambient temperature of 150°C irrespective of the types of UBM. This superior property was attributed to the microstructure change transformed from the solder joint to the IMC joint within the solder micro bump interconnections during electromigration test. All the results of reliability test illustrated that the selection of UBM structure/material well influenced the reliability performance of fine-pitch solder micro bump interconnections in 3D chip stacking.

As device-scaling challenges increase, three-dimensional (3D) integrated circuits (ICs) are receiving more attention for system performance enhancements, due to their higher interconnect densities and shorter interconnect lengths. However, because of the limited contact area and the higher circuit density, the cooling of 3D ICs is more challenging. In order to assess appropriate cooling solutions for 3D chip stacks in various uses, we need better understanding of the total thermal resistance of 3D chip stacks. This calls for precise thermal resistance measurements and thermal modeling for each component of a 3D chip stack. A 3D chip stack is composed of interconnections, silicon substrates, back-end-of-the-line (BEOL), front-end-of-the-line (FEOL) and in this study, the thermal resistance of interconnections is the primary focus because interconnections are regarded as one of the thermal resistance bottlenecks of a 3D chip stack. With regard to the thermal resistance measurements of interconnections, Yamaji et al. found it difficult to measure the thermal resistance of interconnections with the laser-flash method and pointed out that care was necessary for uniform temperature distribution in the sample when using the laser-flash method on heterogeneous specimens, such as stacked chips with interconnections. Considering this concern, we use a steady-state method for the thermal resistance measurements of the interconnections. The thermal resistance of 200μpitch-C4 (Pb97Sn3) joined samples is measured and the thermal conductivity of C4 is derived to be 18 – 24 W/mC. Also the thermal resistance of a silicon with various interconnection pitches and diameters is modeled and the relationship of thermal resistance to interconnection pitch and diameter is obtained. The thermal resistance reduction by underfill with various interconnection pitches and diameters is also studied.

As the demands of functionality and performance for electronic products increase, three-dimensional chip stacking with high-density I/O has received much attention. For high density interconnections packaging, solder micro bumps are adopted extensively. However, its process temperature is high during chip stacking process. High bonding temperature would be easy to lead chip damage and chip warpage. For diminishing the thermal damage resulted from the high bonding temperature during chip stacking, we used the anisotropic conductive film as an intermediate layer to bond the chips. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles was adopted for assembling a chip stack module with a micro bump pitch of 30μm. The reliability of the chip stack assembled by such novel material was evaluated and estimated also. The chip-to-chip stack module having more than 3000 I/Os with a pitch of 30μm was used as the test vehicle. The structure of Cu/Ni/Au micro bump was chosen and fabricated on both the silicon chip and substrate. The silicon chip was bonded onto the silicon substrate using the arrayed-particles ACF material after ACF lamination process. The optimized lamination conditions and the effects of bonding pressure and temperature were evaluated and determined by considering the particle deformation, electrical performance and adhesive flow phenomenon. After optimizing the lamination and bonding parameters, the reliability of the assembled C2C module was evaluated by Pre-condition test, TCT and THST. Cross-sectioned inspection of micro joints by scanning electron microscopy, observation of interface between adhesive and silicon by scanning acoustic tomography, and adhesion test of ACF film after bonding and precondition were conducted to determine the failure modes of the ACF joining. After precondition test, less than 15% of daisy-chain resistance variation was found. The ACF joints with stable electrical resistance could be obtained by such kind of novel material. Also, no any obvious ACF delamination could be observed. The adhesion strength did not show any degradation after precondition test. The reliability test results revealed that the assembled C2C module by the arrayed-particles ACF showed the acceptable reliability performance in TCT and THST. The results of failure analysis displayed that the connectivity of ACF joints was damaged by induced thermal stress coming from the mismatch of CTE between adhesive matrix and conductive particles during environmental testing. This study presented that the arrayed-particles anisotropic conductive film adopted had great potential and could be applied for the 3D chip stacking assembly with fine pitch interconnects.

In order to determine appropriate cooling solutions for 3D chip stacks in various cases, it is important to have a better understanding of the total thermal resistance of a 3D chip stack. For this purpose, precise thermal resistance measurements and modeling of each component of a 3D chip stack are important. The thermal resistance of interconnection is considered to be one of the thermal resistance bottlenecks of a 3D chip stack. In this study, a steady-state thermal resistance measurement method is employed for the thermal resistance measurement of interconnection. The thermal resistance of the 200 μm pitch C4's (Pb97Sn3) jointed samples are measured and the thermal conductivity of C4's is derived to be 18–24 W/mK. With regard to the thermal resistance of a silicon substrate, the thermal resistance of a silicon substrate with various interconnection pitches and diameters has already been modeled by considering the concentrated heat flow to interconnection, as presented in ICEP 2008.[15] Based on the modeled data, the thermal resistance reduction by underfill with various interconnection pitches and diameters is also studied.

Soft errors in microelectronics devices, responsible for the malfunction of electronic systems, have become a hot issue for miniaturized and high-density packaging like three-dimensional (3D) packaging. Low alpha solder generates very few α-radiation-caused errors and malfunction in electronic devices compared with regular solder. It can improve performance and reliability of through-Si-via (TSV) packaging, prompting the need to adopt low alpha solder for bumping in TSV packaging. TSV technology has emerged as a popular choice for 3D packaging and chip stacking. In this study, the bonding properties of low alpha solder on Cu-filled TSV were investigated. TSVs were fabricated in a Si wafer by deep reactiveion etching, and Cu was filled in the via by electroplating using the periodic pulse-reverse current waveform. Cu filling in the via was achieved in 4 h without any defects at a cathodic current density of −8 mA/cm2. The LC-3 class of a low alpha solder ball (alpha emission < 0.05 cph/cm2) having a composition of Sn-1.0 wt.% Ag-0.5 wt.% Cu (SAC105) and a diameter of 80 μm was reflowed on the Cu-filled TSV to form the solder bump. High-speed shear test was performed on the bumped low alpha solder ball to assess the shear strength and to investigate the fracture mode. The shear strength of the low alpha solder bump showed a maximum value of 369.63 mN at 1.0 m/s shearing speed and 17.6 μm tip height. The fraction of brittle fracture increased with increasing shearing speed.

3-D chip-stacking packages and 3-D through silicon via (TSV) vertical interconnection are popular flip-chip assembly methods. Cu-pillar/SnAg micro bumps have usually been used for vertical interconnections in the 3-D TSV chip stacking. These vertical interconnections are fabricated using a thermocompression bonding method with nonconductive films (NCFs). The fabrication heat and pressure lead to molten solder wetting the pad. However, the deformed molten solder on the sidewall of the Cu-pillar results in an increase in solder and Cu-pillar contact interfaces. As a result, more Sn is consumed and Kirkendall voids occur at the solder joint. Novel double-layer NCFs (D-NCFs) can solve the problem of solder wetting the sidewall of the Cu-pillar. D-NCFs are two NCF layers, consisting of a fast-curing top NCF layer and a slower-curing bottom NCF layer. The top NCF layer is designed to have a curing onset temperature below the melting temperature of the solder, to prevent the molten solder wetting the Cu-pillar sidewall. The bottom NCF layer, which has a slower curing property and flux ability, helps the molten solder wet the pads. In this paper, D-NCFs were investigated for the wafer-level (WL) processing of 40- $\mu \text{m}$ fine-pitch Cu-pillar/SnAg micro bump chip assemblies. The D-NCFs properties were first adjusted for WL capability, and then bonding conditions were optimized in terms of solder wetting on the Cu-pillar and electrical interconnection. As a result, the D-NCFs were found to significantly increase the amount of Sn solder remaining between the Cu-pillar/SnAg/Cu interconnection, and also to decrease Sn consumption.

In this study, we developed a Cu paste that can be used as a filling material for through silicon via (TSV), through glass via (TGV), and organic substrates. Non-through holes with diameters ranging between 20 and 100 μm and depths ranging between 70 and 100 μm (aspect ratios from 1 to 3.5) formed in a silicon surface layer were filled with Cu paste. TGV substrates with diameters ranging between 30 and 90 µm and thickness of 300 µm were filled with Cu paste without cracking. Multilayer substrates with the diameters of 180 and 260 µm and a thickness of 6.4 mm (aspect ratios: 25, 36) were filled with Cu paste without cracking. The 2.5D chip package was prepared using a TSV filled with Cu paste as a 2.5D interposer. The 2.5D chip package was verified through reliability test [thermal cycle test (TCT), high temperature storage test (HTST), un-bias high accelerated stress test (HAST) and pressure cooker test (PCT)]. After the reliability test, the conductive resistance of the package that adopted the Cu paste was found to be within 10% of the initial value. Moreover, we found that Cu paste can be applied to 2.5D interposer as filling material.

For the thermal management of three-dimensional (3D) chip stack, its thermal resistance needs to be clearly understood. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. At SemiTherm2011, the equivalent thermal conductivity of the interconnection, including BEOL (Back-End-Of-the-Line, wiring layer) is experimentally obtained to be 1.6W/mC and this time, we measure the thermal effect of Cu TSVs and it is experimentally supported that as the Cu TSV area ratio increases, the thermal conductivity of chip with TSVs in the vertical direction increases, on the contrary, that in the horizontal direction decreases. Also, the transient thermal measurement is performed and its result is compared with steady state measurement result. Further, the thermal capacitance measurement of 3D stacked test chip with hot spot heating is performed, which is essential to determine the transient thermal performance of 3D chip stack.

The governing factors of copper wirebond failures under high humidity conditions were experimentally elucidated on the basis of the results of intermetallic compound (IMC) analysis using Scanning Transmission Electron Microscope (STEM). The IMC behavior at the bonding interface under high temperature storage (HTS) test and pressure cooker test (PCT) have been examined and compared. The results of HTS and PCT suggested that the main factor causing the Cu wirebond failures under PCT condition is not a growth of brittle IMC but a corrosion of IMC (Cu9Al4), which is mainly produced during assembly processes and susceptible to corrosion. Result of EPMA mapping for the pad-surfaces on the failure chip indicated that the corrosion is induced by halogen (Cl) in the vicinity of the bonding interface under high humidity condition. The effect of Pd coating and characteristics of mold resin are also discussed on the basis of STEM analysis of the IMC formation and FEM analysis of the thermal stress at the bonding interface.

In this paper, Cu/SnAg double-layered bumps structure was proposed and investigated for the fine pitch flip chip applications. Test chip was designed considering the recent high speed memory device and its pad size and pitch was 60/spl mu/m and 100/spl mu/m, respectively. Cu and SnAg bumps were fabricated as a 60/spl mu/m and 20/spl mu/m thickness on SiO/sub 2//Ti/TiN/Al/TiW/Cu on Si wafer using the electroplating method. Test chip was flip chip assembled with PCB substrates using thermo-compression bonding method. Because the pitch was very tight, the flip chip bonding of Cu/SnAg double bumps was very difficult and it affected several bonding parameters such as bonding pressure, temperature, time, Cu bump diameter and so on. The bonding results were evaluated through the cross-sectional image of interconnection and the electrical continuity test of daisy chain and bump resistance using 4-point Kelvin structure. The long time reliability tests like thermal cycling test and 85/spl deg/C/85% test are now in progress after flip chip bonding and underfill dispensing.

A novel way of three dimensional (3D) chip stacking has been designed in a view to improve heat dissipation across the layers. Solder-based self assembled (SBSA) structures have been designed as 3D posts on simulated through silicon vias to demonstrate the concept. The fabrication of SBSA structures using a low temperature solder alloy and dip soldering method is described. Previously, two types of soldering—face soldering and edge soldering—were studied to fabricate SBSA structures. Face soldering refers to deposition of solder on the complete metal face whereas edge soldering refers to selective deposition of solder on only the edges of the metal face. Mechanical grinding of the 3D structures shows that face soldered SBSA structures were void free and robust enough to be used as a connection post for chip stacking. Edge soldered SBSA structures collapsed when grinding was performed. This suggests the edge soldered 3D structure may only be partially filled. Face soldered SBSA structures provide a solder bump that serves as a connection path in the integration of dissimilar electronic technologies. Cylindrical copper posts, developed in a previous project, can be an effective approach to integrated circuit stacking. However, the SBSA post provides more variety in size and shape and can serve as a reservoir for solder to aid in chip bonding. The solder bumps are heat resistant, and uniform thicknesses were obtained across a large array of SBSA structures. The electrical durability of SBSA posts were determined by completing I-V measurements after thermal treatment. SBSA posts were subjected to thermal cycling with temperatures ranging from room temperature to 300 °C. The interconnected SBSA posts are shown to be stable until 165 °C with little variation in measured resistance.

Current DRAM advanced chip stack packages such as the high bandwidth memory (HBM) use throughsilicon-via (TSV) and thermal compression bonding (TCB) of solder capped micro bumps for the inter-layer connection. The bonding process has low throughput and cannot overcome the challenge of scaling below 40 μm pitch. These are compelling reasons to seek an alternative approach such as hybrid bonding. The pursuit of fine pitch die stacking with TSV interconnect using hybrid bonding is pervasive in the packaging industry today due to the promise of improved performance. Specifically, the Cu interconnect provides improved thermal and electrical performance and the all inorganic interface of the complete die stack offers enhanced thermal-mechanical performance and reliability in the final chip stack. Direct Bond Interconnect technology, also known as low temperature hybrid bonding, forms a spontaneous dielectric-to-dielectric bond at room temperature and then establishes metal-to-metal connection (usually Cu-to-Cu bond) by a low temperature batch annealing process (150 - 300°C). The direct bond process eliminates the need for solder and underfill and associated problems. While the hybrid bonding exists today in wafer-towafer (W2W) format in high volume manufacturing, chip to wafer (C2W) bonding developed for future product lines is making significant process in the past three years. A bonding process with high throughput has been demonstrated with electrical test yield above 90% with a daisy chain structure that covers 50mm^2 of bonding area. The bonded parts showed superior reliability performance in temperature cycling, high temperature storage and autoclave testing. This paper presents the latest development in C2W hybrid bonding and demonstrates the low temperature annealing capability and integration with TSV

To meet future requirements for cost, size, weight and electrical performance, microelectronic packaging is moving from wire bonds to solder bumps as the preferred method of interconnection from the device to the chip carrier or card. Flip chip in package (FCiP) requires many small bumps on tight pitch whereas wafer level chip scale packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. Electroplating, solder paste printing and the direct attach of preformed solder spheres are technologies commonly used in volume production for wafer bumping. Each of these techniques has limitations in scaling from fine pitch FCiP to WLCSP. Electroplating is better suited to fine pitch, whereas solder paste printing and solder sphere attachment work well for coarser pitches. C4NP (controlled collapse chip connection new process) has proven to be suitable for this entire range of solder bump pitch. C4NP is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications. This paper summarizes the latest manufacturing and reliability data for high-end logic device packaging using 300mm wafers bumped with C4NP. This includes initial reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. Mold fill data for CSP type dimensions is included. Solder metrology data and yield information for fine pitch applications is summarized. Relevant process equipment technology and the unique requirements to run a high volume manufacturing C4NP process are reviewed. The paper also summarizes the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is provided by IBM's packaging operations at the Hudson Valley Research Park in East Fishkill, NY and Bromont, Quebec