Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements

As device-scaling challenges increase, three-dimensional (3D) integrated circuits (ICs) are receiving more attention for system performance enhancements, due to their higher interconnect densities and shorter interconnect lengths. However, because of the limited contact area and the higher circuit density, the cooling of 3D ICs is more challenging. In order to assess appropriate cooling solutions for 3D chip stacks in various uses, we need better understanding of the total thermal resistance of 3D chip stacks. This calls for precise thermal resistance measurements and thermal modeling for each component of a 3D chip stack. A 3D chip stack is composed of interconnections, silicon substrates, back-end-of-the-line (BEOL), front-end-of-the-line (FEOL) and in this study, the thermal resistance of interconnections is the primary focus because interconnections are regarded as one of the thermal resistance bottlenecks of a 3D chip stack. With regard to the thermal resistance measurements of interconnections, Yamaji et al. found it difficult to measure the thermal resistance of interconnections with the laser-flash method and pointed out that care was necessary for uniform temperature distribution in the sample when using the laser-flash method on heterogeneous specimens, such as stacked chips with interconnections. Considering this concern, we use a steady-state method for the thermal resistance measurements of the interconnections. The thermal resistance of 200μpitch-C4 (Pb97Sn3) joined samples is measured and the thermal conductivity of C4 is derived to be 18 – 24 W/mC. Also the thermal resistance of a silicon with various interconnection pitches and diameters is modeled and the relationship of thermal resistance to interconnection pitch and diameter is obtained. The thermal resistance reduction by underfill with various interconnection pitches and diameters is also studied.

In order to determine appropriate cooling solutions for 3D chip stacks in various cases, it is important to have a better understanding of the total thermal resistance of a 3D chip stack. For this purpose, precise thermal resistance measurements and modeling of each component of a 3D chip stack are important. The thermal resistance of interconnection is considered to be one of the thermal resistance bottlenecks of a 3D chip stack. In this study, a steady-state thermal resistance measurement method is employed for the thermal resistance measurement of interconnection. The thermal resistance of the 200 μm pitch C4's (Pb97Sn3) jointed samples are measured and the thermal conductivity of C4's is derived to be 18–24 W/mK. With regard to the thermal resistance of a silicon substrate, the thermal resistance of a silicon substrate with various interconnection pitches and diameters has already been modeled by considering the concentrated heat flow to interconnection, as presented in ICEP 2008.[15] Based on the modeled data, the thermal resistance reduction by underfill with various interconnection pitches and diameters is also studied.

As the demands of functionality and performance for electronic products increase, three-dimensional chip stacking with high-density I/O has received much attention. For high density interconnections packaging, solder micro bumps are adopted extensively. However, its process temperature is high during chip stacking process. High bonding temperature would be easy to lead chip damage and chip warpage. For diminishing the thermal damage resulted from the high bonding temperature during chip stacking, we used the anisotropic conductive film as an intermediate layer to bond the chips. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles was adopted for assembling a chip stack module with a micro bump pitch of 30μm. The reliability of the chip stack assembled by such novel material was evaluated and estimated also. The chip-to-chip stack module having more than 3000 I/Os with a pitch of 30μm was used as the test vehicle. The structure of Cu/Ni/Au micro bump was chosen and fabricated on both the silicon chip and substrate. The silicon chip was bonded onto the silicon substrate using the arrayed-particles ACF material after ACF lamination process. The optimized lamination conditions and the effects of bonding pressure and temperature were evaluated and determined by considering the particle deformation, electrical performance and adhesive flow phenomenon. After optimizing the lamination and bonding parameters, the reliability of the assembled C2C module was evaluated by Pre-condition test, TCT and THST. Cross-sectioned inspection of micro joints by scanning electron microscopy, observation of interface between adhesive and silicon by scanning acoustic tomography, and adhesion test of ACF film after bonding and precondition were conducted to determine the failure modes of the ACF joining. After precondition test, less than 15% of daisy-chain resistance variation was found. The ACF joints with stable electrical resistance could be obtained by such kind of novel material. Also, no any obvious ACF delamination could be observed. The adhesion strength did not show any degradation after precondition test. The reliability test results revealed that the assembled C2C module by the arrayed-particles ACF showed the acceptable reliability performance in TCT and THST. The results of failure analysis displayed that the connectivity of ACF joints was damaged by induced thermal stress coming from the mismatch of CTE between adhesive matrix and conductive particles during environmental testing. This study presented that the arrayed-particles anisotropic conductive film adopted had great potential and could be applied for the 3D chip stacking assembly with fine pitch interconnects.

In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through Si via connections were formed by UV laser drilling technology. Laser drilling is a non-contact manufacture method and laser beam with high energy can be focused to a small spot (15 mum beam diameter) for material ablating and removing without mask used. Several processes are the keys to accomplish 3D stacking, such as wafer thinning process, through silicon via forming process, dielectric layer forming process, metallization process, and inter chips bonding process. By integration of the mentioned key processes, a 3D chip stacking structure with 10 layers was carried out. The thickness of chip was 100 mum. Daisy chain pattern was designed for the electrical measurement of 3D stacking structure. The testing results show that the resistance of multi- chip stacking structure is about 0.056 Omega/cm. Some reliability test, such as temperature cycling test and pressure cooker test were also done. These testing results verified this PCB processing compatible 3D chip stacking technology with low cost is a reliable structure for 3D SiP (System in Packaging) module application.

Three-dimensional (3D) chip stacking architecture is expected to reduce form factor, improve performance, and decrease power consumption in future microelectronics. High power density and nonuniform power distribution in stacked dies are expected to bring significant thermal challenges for 3D packages due to localized hot spots. Embedded thermoelectric coolers (TECs) have potential to provide reliable and localized cooling at these hot spots. In this work, peak package temperature or active cooling per power consumption of TECs are optimized, considering applied current and thickness of TECs as parameters, for a 3D electronic package with two stacked dies. Each die has two hot spots and one TEC is paired with each hot spot. Three different optimization methods are considered in order to ensure a robust solution. The optimization suggests that both the peak temperature in package and energy efficiency of the cooling system can be significantly improved through the optimization of TECs. TECs are also compared against a configuration where they are replaced by copper blocks or thermal vias. A total of 4.7 °C of additional localized cooling is observed using TECs which is beyond what is achievable with copper vias in place of the TECs. The study also suggests that it is better to use TECs to cool only the hottest portions of the package to avoid introducing additional thermal resistance and Joule heating in the package.

Three-dimensional (3D) chip stacking is a promising approach for high performance microsystems. Such vertical integration could increase the clock frequency and reduce the signal delay. During operation, the input signal and the resulting input power change with time. Realistic power maps on active chip tiers produce highly non-uniform heat flux patterns with hotspots, which change with time. In this paper, a transient compact model of a multi-layer chip stack subjected to time dependent power map was developed. Inter-tier single phase microfluidic cooling with a pin fin array was used to enhance heat transfer. The validity of the compact model was confirmed by comparison with full computational fluid dynamics/heat transfer (CFD/HT) modeling. It was found that the transient compact model ran thousand times faster than the CFD/HT model. The maximum deviation between the two models was 1 °C. The compact model was then used to analyze the transient thermal response of a 4 layer dual core stack of Penryn microprocessors when a total power of 172.4 W with a 300 W/cm2 hot spot was suddenly applied. The hotspot temperature rise approaches 35 °C, at a steady state time of about 0.015 s. The temperature rise of bottom tier was always higher than the other three tiers during the transient process because it has only single side cooling, while other tiers have double sided cooling. Also, different power maps and flow patterns, including parallel and counter flow for different layers were investigated. It was found that controlling the flow in different layers individually instead of applying the same flow conditions could achieve better thermal performance and energy savings.

Three-dimensional (3D) LSI chip stacking with through chip electrodes can realize high-density packaging and high-speed operation performance because the through chip electrode offers the shortest interconnection between stacked chips. The through chip via size we studied was 10 /spl mu/m-square and 70 /spl mu/m-deep. The void free plating is necessary to avoid problems caused by acid solutions remaining in voids. In this paper, systematic studies of the dependence of electroplating conditions on via filling are described. We found that vias could be almost filled completely.

With the increased demand of functionality in electronic device, three dimensional integration circuits technology together with downscaling of interconnection pitch present an important role for the development of next generation electronics. In the current types of interconnects, solder micro bumps have received much attention due to its low cost in material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the UBM structure/material will show a significant influence on the reliability performances of the solder micro bump joints. However, which UBM structure/material for fine pitch solder micro bump joint presents the better reliability properties is not concluded yet until now. In this study, the effect of UBM structural/material on the reliability properties of lead-free solder micro interconnections with a pitch of 30μm was discussed. The chip-on-chip test vehicle with solder micro bump interconnections having a diameter of 18 μm was adopted to evaluate the effects of UBM structure/material. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. In this study, three types of UBM were selected on the silicon carrier: they were single copper layer with a thickness of 8μm; the Cu/Ni layer with the thickness of 5μm/3μm and the Cu/Ni/Au layer with the thickness of 5μm/3μm/0.5μm. The UBM was electro-plated on the Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. For the silicon carrier with the bump structure of Cu/Sn and Cu/Ni/Sn, the silicon test chip with solder micro bump of Cu/Sn was used for chip bonding. The test chip having the solder micro bump of Cu/Sn and Cu//Ni/Sn was used for bonding with the silicon carrier having the Cu/Ni/Au UBM. In chip stacking process, we adopted the fluxless thermocompression process for each type of micro joints. After chip bonding process, the fine gap between bonded chips was filled by capillary type of underfill. The influence of underfill on the reliability of solder micro bump interconnects with various combinations of UBM structures were estimated also. After the assembly process, temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were performed on the chip-stacking module to assess the effect of UBM structure/material on the reliability of solder micro bump interconnections. The results of reliability test revealed that only Cu/Sn/Au/Ni/Cu micro joint could not pass the TCT and HTS of 1000 cycles. After reliability test, the Cu/Sn/Cu joints showed the evidently microstructural evolution while the Cu/Ni/Sn/Cu joints did not show apparent microstructure change among all the types of micro joints and still revealed the most contents of residual solder within the joint. On the other hand, the existence of Au layer upon the UBM caused the complicated interface reaction between solder and UBM, which presented a negative effect during long-term reliability performance. The reliability results also displayed that the introduction of underfill could apparently enhance the reliability of micro joint under mechanical evaluation. From the results of EM reliability test, all the types of the micro joints showed excellent electromigration resistance under current stress of 0.08A at an ambient temperature of 150°C irrespective of the types of UBM. This superior property was attributed to the microstructure change transformed from the solder joint to the IMC joint within the solder micro bump interconnections during electromigration test. All the results of reliability test illustrated that the selection of UBM structure/material well influenced the reliability performance of fine-pitch solder micro bump interconnections in 3D chip stacking.

Multi-layer 3D chip stacking by a surface-tension-driven self-assembly technique is demonstrated. After multi-layer self-assembly, memory chips having Cu-SnAg μbump and Cu-TSVs are bonded on a substrate by thermal compression to confirm electrical joining between them. In addition, we investigate the impacts of wetting properties of chip/substrate surfaces, μbump shapes, and μbump layout on alignment accuracies of self-assembly. Good electrical characteristics are obtained from the TSV-μbump daisy chains in the stacked memory chips.

Cooling of a planar 2D IC chip utilizes heat transfer from a face of the chip though a heat sink. In case of a 3D IC chip stack, the individual chip faces are not available for mounting conventional heat sinks. Mounting the heat sinks on the ends is feasible, but the heat flow paths for the interior chips from the junction to the heat sink become longer. Further, multiple heat sources present along the heat flow paths in stacked chips may create localized hot spots which exceed the allowable junction temperatures. While 2.5D integration in complex ICs where individual layers are mounted on another base die called an interposer can alleviate the heat dissipation issues, it cannot deliver the benefits of monolithic 3D ICs due to the planar distance between the chips or chiplets over the interposer. Introducing interlayer cooling with microchannels and introducing fins in the coolant flow paths extend the thermal dissipation capability of a 3D stack; however this is often accompanied with taller microchannels that lead to longer lengths of through-silicon-vias (TSVs). Placement of TSVs, microchannels walls and fins present conflicting design requirements. Therefore co-design and innovative approaches are seen as critical before widespread commercialization of 3D ICs becomes a reality. An overview of the available cooling options for 3D ICs and their performance evaluation are presented in this chapter.

Requirements of a quantum beam imager such as a vertex detector in high energy physics experiment are intelligent functions which are realized by embedding memories of quantum beam hit-position, hit-charge, and hit-timing in a pixel with keeping small pixel size to achieve high spatial resolution. To satisfy the requirements, circuit layer stacking on a sensor, i.e., three dimensional (3D) technology, has been widely studied and proposed. The Silicon-on-Insulator (SOI) sensor is one of the 3D sensors because the circuits in the top silicon layer is on the sensors of the bottom silicon substrate. The circuits and sensors are electrically connected by submicron W filled vias through the buried oxide (BOX), which are called as through BOX vias (TBV). Thus, the SOI sensor has extremely higher fill factor than the bulk-CMOS sensor. In order to achieve more intelligent functions in the pixel, however, the pixel size by using the simple SOI technology is large to get the required spatial resolution. Therefore, multiple circuit layer formation by chip stacking technology is adopted. In this chip stacking, a fine pitch micro-bump technology with two-tile face-to-face stacking is employed because of the simplest 3D structure. The target of micro bump diameter and spacing are 2.5 μm and 5 μm, respectively. The SOI 3D chip stacking process is starting with the base chips which are fabricated by an 8 inch 0.2 μm fully depleted SOI pixel sensor process with five metal layers. After the metal 5 etching, an oxide film is deposited and planarized by chemical mechanical polishing (CMP). W-filled vias to a under bump metal is formed at bump formation areas. After the under bump metal deposition and patterning, metal bumps are formed. Then, two chips which are lower and upper chips are aligned and bonded face-to-face at 200℃ followed by adhesive injection. To make bonding pads on the upper chip, the upper chip handle silicon is etched until exposing the BOX and TBV by wet solution. TBV can easily connect between circuits in the upper chip and the bonding pad metal without any through silicon via (TSV) process. This is the most superior point to use the FD-SOI pixel sensor in 3D structure. The TBV size is around 0.3 μm which is much smaller than a conventional TSV whose size is around 5 μm by using the most advanced technology. In addition, this TBV can be used as interconnections between multiple chips without any TSV. Finally, bonding pad and passivation formation are done. For micro bump formation, a gold bump was utilized because the gold is oxidation-resistant metal. The micro gold bump was fabricated by two methods. One is a cone shaped gold bump manufactured by a gold nanoparticle deposition with a photoresist lift-off technique [1]. The cone shaped gold bump with 2.5 μm in diameter and 2.5 μm in height are successfully formed on the under bump metal layer. Because of the nanoparticle deposition, the gold bump is easier to deform by the bonding. Thus, the collapsibility allows low stress to the die and high reliable junctions. It is also confirmed that the bump resistance is approximately 0.25 Ω/bump from daisy chain measurement. The other is a gold cylindrical bump using a combination of inverse-tapered photoresist and low incident angle sputtering [2]. Because of narrowing at the top, lower pressure to collapse between the bumps is required than the gold cone bumps. This may also improve bump yield and reliability. 0.37 Ω/bump of the bump resistance is obtained by the gold cylindrical bumps. Using the FD-SOI 3D chip stacking technology with the cylindrical bump, the pixel sensor designed for the International Linear Collider (ILC) vertex detector called SOFIST was fabricated and the chip photo is shown in the figure. In SOFIST, hit-position, hit-charge, and hit-time memories are embedded in each pixel by the 3D micro bump bonding with 20 mm pixel size. Owing to the removal of the handle silicon of the upper chip, the patterns of the lower chip can be seen through the upper chip oxide. The green patterns close to bonding pads are backsides of silicon layer in the upper chip. As shown in the figure, our 3D process technology is successfully introduced in FD-SOI quantum beam imager.

The threat of food safety and the limited analytical methods with high performance promote the growing interest in the development of pathogenic bacteria biosensors. This study presents a pathogenic bacteria biosensing system, where a novel three-dimensional (3D) chip acts as an analytical carrier and DNA-programmed hybridization chain reaction (HCR) causes signal amplification. The 3D chip is designed featuring a compact multichannel structure. It has a large surface area for sensitive sensing and exhibits multiple functions of target capture, separation, rinsing, and signal detection to simplify the analysis processes. HCR, which enables the fluorophore's polymerization, is designed as two signal amplification modes, each with unique advantages. Mode I achieves highly sensitive detection in a "sandwich" assay format, in which a long HCR-amplified probe is used to boost the fluorescence signal. In mode II, the assembly of HCR is performed on the inner surface of the 3D chip. Especially, a group of rapid-assembly HCR sequences is proposed, of which the assembly time as short as 15 min stands out among the related works previously reported. Under the optimal conditions, the proposed biosensing system has the limits of detection (LOD) of 4 and 8 cfu/mL in mode I for Staphylococcus aureus detection and in mode II for Salmonella enterica Typhimurium detection, respectively. The specificity and the real sample applications are evaluated. This multichannel-structured 3D chip based on HCR signal amplification has potential applications in food safety monitoring and biosensor development.

HotSpot is an open source analysis tool for estimating temperature of both 2D and 3D chip stacks. It counts both the primary path of the heat transfer through the heat-sink and the secondary path through the print circuit board. It can estimate the temperature of chips. However, HotSpot-6.0 cannot treat a complicated chip stacking such as the castle of chips (CoC) with inductive wireless coupling through-chip interface (TCI). Therefore, in this report we have extended the HotSpot simulator and updated it in order to evaluate CoC. Compared to the original HotSpot, the extended version of HotSpot had an average execution time increase of about 6% when evaluating the same vertical stacking. The execution time of CoC with the same number of chips is shorter than when executing vertical stacking, but when the number of layers is the same, the execution time is almost equal. Moreover, our design considers high productivity, e.g. it can easily set air cooling, oil cooling, water cooling evaluation and chip rotation setting.

Soft errors in microelectronics devices, responsible for the malfunction of electronic systems, have become a hot issue for miniaturized and high-density packaging like three-dimensional (3D) packaging. Low alpha solder generates very few α-radiation-caused errors and malfunction in electronic devices compared with regular solder. It can improve performance and reliability of through-Si-via (TSV) packaging, prompting the need to adopt low alpha solder for bumping in TSV packaging. TSV technology has emerged as a popular choice for 3D packaging and chip stacking. In this study, the bonding properties of low alpha solder on Cu-filled TSV were investigated. TSVs were fabricated in a Si wafer by deep reactiveion etching, and Cu was filled in the via by electroplating using the periodic pulse-reverse current waveform. Cu filling in the via was achieved in 4 h without any defects at a cathodic current density of −8 mA/cm2. The LC-3 class of a low alpha solder ball (alpha emission < 0.05 cph/cm2) having a composition of Sn-1.0 wt.% Ag-0.5 wt.% Cu (SAC105) and a diameter of 80 μm was reflowed on the Cu-filled TSV to form the solder bump. High-speed shear test was performed on the bumped low alpha solder ball to assess the shear strength and to investigate the fracture mode. The shear strength of the low alpha solder bump showed a maximum value of 369.63 mN at 1.0 m/s shearing speed and 17.6 μm tip height. The fraction of brittle fracture increased with increasing shearing speed.

A novel way of three dimensional (3D) chip stacking has been designed in a view to improve heat dissipation across the layers. Solder-based self assembled (SBSA) structures have been designed as 3D posts on simulated through silicon vias to demonstrate the concept. The fabrication of SBSA structures using a low temperature solder alloy and dip soldering method is described. Previously, two types of soldering—face soldering and edge soldering—were studied to fabricate SBSA structures. Face soldering refers to deposition of solder on the complete metal face whereas edge soldering refers to selective deposition of solder on only the edges of the metal face. Mechanical grinding of the 3D structures shows that face soldered SBSA structures were void free and robust enough to be used as a connection post for chip stacking. Edge soldered SBSA structures collapsed when grinding was performed. This suggests the edge soldered 3D structure may only be partially filled. Face soldered SBSA structures provide a solder bump that serves as a connection path in the integration of dissimilar electronic technologies. Cylindrical copper posts, developed in a previous project, can be an effective approach to integrated circuit stacking. However, the SBSA post provides more variety in size and shape and can serve as a reservoir for solder to aid in chip bonding. The solder bumps are heat resistant, and uniform thicknesses were obtained across a large array of SBSA structures. The electrical durability of SBSA posts were determined by completing I-V measurements after thermal treatment. SBSA posts were subjected to thermal cycling with temperatures ranging from room temperature to 300 °C. The interconnected SBSA posts are shown to be stable until 165 °C with little variation in measured resistance.