80186 c compiler

Scandinavian firms choose DR personal s/w

Hardware software co-design plays a crucial part in the embedded processor development especially with the current advancement of reconfigurable platforms. The reconfigurability features offered by platforms such as Field Programmable Gate Array (FPGA) has permitted the modification of the internal processor architecture with lower cost and higher performance. While the hardware architecture could be changed through various methods, the modifications need to be complemented with a compatible assembler that suits the amended architecture. This paper presents a two-pass assembler design technique that adapts to any instruction set architecture (ISA) modifications being applied on a reconfigurable processor. A Reduced Instruction Set Computer (RISC) processor core, which is described in Verilog Hardware Description Language (HDL), is used as the testing platform whereby its ISA is expanded to include new instruction sets. The assembler is developed based on two-pass approach and the assembling process would generate a coefficient file that is used as initialization files during the FPGA implementation of the processor core. The assemblers have been successfully developed with correct output format and verified during the FPGA implementation using Xilinx Spartan-3AN board.

Chapter 17 explores the fundamentals of the x86-64 core architecture. It begins with an overview of its internal architecture, which includes details of the execution units, general-purpose registers, instruction operands, and memory addressing modes. Next is a discussion of the differences between the x86-64 and x86-32 execution environments that programmers need to be aware of when coding assembly language functions. The final section of this chapter encapsulates the x86-64 instruction set. All of the material in this chapter assumes that you have a basic understanding of the x86-32 core architecture and the x86-32 instruction set.

12 - The next generations

This paper presents the architecture and field-programmable gate array (FPGA) implementation of a 32-bit central processing unit (CPU) dedicated to programmable logic controllers (PLCs). The CPU instruction set directly matches the instructions of the IEC 61131-3 standard Instruction List (IL) language. The designed IL processor is capable of handling 1-bit, 8-bit, 16-bit, and 32-bit data types. Apart from integer arithmetic operations, the IL processor also performs single precision floating-point operations included in the IEC 61131-3 IL language specification. It also directly performs instructions with a parenthesis modifier for all supported data types and facilitates the fast execution of a code containing Boolean expressions. This paper also presents the performance evaluation results of the developed IL processor. Although the IL processor executed the test algorithms substantially faster than industrial PLCs (e.g., Siemens S7-1200 and Fanux VersaMax), it turned out to be significantly slower than high-performance programmable automation controllers (PACs).

This paper investigates the state estimation problem of power systems. A novel, fast and accurate state estimation algorithm is presented to solve this problem based on the one-dimensional denoising autoencoder and deep support vector machine (1D DA–DSVM). Besides, for further reducing the computation burden, a partitioning method is presented to divide the power system into several sub-networks and the proposed algorithm can be applied to each sub-network. A hybrid computing architecture of Central Processing Unit (CPU) and Graphics Processing Unit (GPU) is employed in the overall state estimation, in which the GPU is used to estimate each sub-network and the CPU is used to integrate all the calculation results and output the state estimate. Simulation results show that the proposed method can effectively improve the accuracy and computational efficiency of the state estimation of power systems.

Reduced Instruction Set Computing (RISC) processors have wide selection of applications performance on speed and better cache memory. The advanced RISC microprocessors are extensively used for many of the complicated systems. Reduced Instruction set Computing (RISC) is a CPU (Central Processing Unit) design mechanism that displays fundamental instruction set and performs better after comparison with the other microprocessor architecture and has the ability to perform commands per instruction through microprocessor cycles. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. Building of a fully synthesizable 32-bit RISC processor with Fetching unit, Decoding unit, Data and instruction memory, and Execution unit. The RISC Processor design is synthesized and implemented using Xilinx ISE Tool and simulated using I-sim. A 32-bit RISC is simulated and checked through VIO IP cores. We can use debug feature to drive and monitor signals that are present on the real hardware. This work is intended with Verilog HDL and implemented with the help of development board using Artix-7 FPGA device. The outcomes of performance are evaluated in terms of area, timing performance and maximum frequency of operation. The RISC processor compares earlier comparable architecture with efficient developments.

Cryptographic algorithms are widely used as the foundation of various security systems and applications (e.g., secure communication, blockchain systems, and cloud services). A block cipher is an essential cryptographic algorithm to achieve confidentiality. This paper proposes parallel implementations of Korean block ciphers using Advanced Vector eXtension (AVX)-512, which is a new Single instruction, multiple data (SIMD) instruction set that has recently been integrated into several high-end Intel central processing unit (CPU). Target algorithms are LEA, HIGHT, and CHAM block ciphers. Additionally, this paper also proposes applicable implementing techniques, which are designed for each algorithm. These enable to use of parallel processing instructions in AVX-512 properly for each algorithm. The proposed LEA-128 (192, 256 resp.)implementation demonstrates a performance improvement of 506.09% (323.31%, 386.76% resp.) compared to the reference code, and our HIGHT implementation exhibits a performance improvement of 520.88% compared to the reference code. In addition, CHAM-64/128 (128/256 resp.) implementation shows a performance improvement of 1,325.81% (833.61% resp.) compared to the reference code. In addition, we measured the performance with a 32MB long message. LEA-128 (192, 256 resp.) implementation showed an improvement of 556.32% (594.74%, 615.38% resp.) compared with the reference code. Also, HIGHT implementation showed 834.40%, and CHAM showed 1,332.40% (832.86% resp.) for CHAM-64/128 (CHAM-128/256 resp.), compared by the reference code. To the best of our knowledge, this is the first result of the study to optimize Korean cryptographic algorithms using the AVX-512 instruction set. The proposed methods can effectively be used in Addition, Rotation, and XOR (ARX)-based cryptographic algorithms, enabling efficient cryptographic algorithm processing in various environments such as hash-based signatures, service environments, gateway, and edge computing.

In radiation transport calculations, the effects of material temperature on neutron/nucleus interactions must be taken into account through Doppler broadening adjustments to the microscopic cross section data. Historically, Monte Carlo transport simulations have accounted for this temperature dependence by interpolating among precalculated Doppler broadened cross sections at a variety of temperatures. More recently, there has been much interest in on-the-fly Doppler broadening methods, where reference data is broadened on-demand during particle transport to any temperature. Unfortunately, Doppler broadening operations are expensive on traditional central processing unit (CPU) architectures, making on-the-fly Doppler broadening unaffordable without approximations or complex data preprocessing. This work considers the use of graphics processing unit (GPU)s, which excel at parallel data processing, for on-the-fly Doppler broadening in continuous-energy Monte Carlo simulations. Two methods are considered for the broadening operations – a GPU implementation of the standard SIGMA1 algorithm and a novel vectorized algorithm that leverages the convolution properties of the broadening operation in an attempt to expose additional parallelism. Numerical results demonstrate that similar cross section lookup throughput is obtained for on-the-fly broadening on a GPU as cross section lookup throughput with precomputed data on a CPU, implying that offloading Doppler broadening operations to a GPU may enable on-the-fly temperature treatment of cross sections without a noticeable reduction in cross section processing performance in Monte Carlo transport codes.

The Advection-Diffusion Reaction (ADR) equation appears in many problems in nature. This constitutes a general model that is useful in various scenarios, from porous media to atmospheric processes. Particularly, it is used at the interface between two fluids where different types of instabilities due to surface mobility may appear. Together with the ADR equation, the Darcy-Brinkman model describes the phenomena known as fingering that appear in different contexts. The study of this type of system gains in complexity when the number of chemical species dissolved in both fluids increases. With more solutes, the increasing complexity of this phenomenon generally requires much computational power. To face the need for more computational resources, we build a solver tool based on an Alternating Direction Implicit (ADI) scheme that can be run in Central Processing Unit (CPU) and Graphic Processing Unit (GPU) architectures on any notebook. The implementation is done using the MATLAB platform to compare both versions. It is shown that using the GPU version strongly saves both resources and calculation times.

This paper proposes a novel imaging approach for damage identification in structural components. Improvements to conventional Synthetic Aperture Focus (SAF) algorithms are introduced by exploiting multiple wave propagation modes (longitudinal and shear) in the bulk of the material. Significant reduction of artifacts is achieved through the application of adaptive weights based on the wave mode structure and the coherent compounding of longitudinal and shear waves. Further improvement can be achieved by introducing various signal processing techniques, such as baseline subtraction and deconvolution of the point spread function. Finally, utilizing the massively parallel processing structure of a Graphical Processing Unit (GPU) architecture, a considerable increase in speed can be achieved compared to a traditional serial processing technique based on a Central Processing Unit (CPU). A 64-element linear array connected to a data acquisition system was used for experimental validation of the proposed tomographic algorithm steps. Results will be shown from tests performed on rail sections with simulated and natural flaws acquired from the Federal Railroad Administration (FRA) rail defect library. Considerable reduction of side lobes and improvement of image contrast are demonstrated. Future extensions of this work are also investigated, including guided wave inspection in a multi-mode environment and high-speed inspections.

Introduction: The evolution of precision oncology will demand the integration of multi-omics, clinical data, demographics and outcomes, which is a complex and computationally intensive endeavor. Accurate and robust molecular characterization of pediatric leukemias require a comprehensive approach involving longitudinal sample collection across a large cohort. Genomic alterations, both germline and somatic, need to be efficiently captured and annotated to identify clinically meaningful trends. Algorithms developed for conducting genomic analysis typically leverage a central processing unit (CPU) environment for data processing and traditional statistical approach, such as Bayes' theorem, for variant detection. More recently, algorithms have been developed that can leverage a graphics processing unit (GPU) architecture and machine learning (ML) technology. In this study we benchmarked these techniques and applied them sequencing data generated from pediatric AML subjects enrolled on the Children's Oncology Group AAML1031 trial (951 samples). Methods: Whole genome sequencing was conducted using the Illumina platform (2X150) and sequenced between 30x-60x coverage. Genome alignment files were generated and subjected to germline and somatic variant calling (NVIDIA's Selene DGXA100 cluster; Parabricks Pipelines). Germline variants were called using Haplotype caller and DeepVariant (Parabricks v3.0). HG002 genome in a bottle sample was used as a positive control to determine precision, recall and F1 score. Somatic variant calling was completed using somatic sniper, VarScan2, Muse, MuTect2, and Strelka (Parabricks v3.5) and SEQCII data was used to assess somatic variant calling performance. Results: Control sample HG002 was used for benchmarking the algorithms tested. At all depths analyzed, 50X, 30X, 15X, and 5X, GoogleDeep Variant had the highest F1 score, precision, and recall compared to Haplotyper for SNPs and InDels. For somatic SNV detection using SEQCII dataset, Strelka2 had the highest F1 score, precision, and recall (0.9435, 0.9445, 0.9425), followed by MuTect2, MUSE, VarScan2, and SomaticSniper. For somatic InDel detection, MuTect2 and Strelka2 performed similar with MuTect2 higher precision, but Strelka2 had higher recall. These pipelines were utilized to analyze 951 pediatric AML samples, and demonstrated superior processing time and identification of variants, both germline and somatic. Discussion: ML algorithms integrated into a GPU computing environment demonstrated greater precision and accuracy for germline variant detection compared to traditional statistical approaches for variant detection. Ongoing efforts are focused at integration of multiple data sources correlated with outcomes and analyzed via ML tools in order to improve future risk stratification and therapeutic selection for superior outcomes. Citation Format: Erin L. Crowgey, Pankaj Vats, Karl Franke, Gary Burnett, Ankit Sethia, Timothy Harkins, Todd E. Druley. Enhanced processing of genomic sequencing data for pediatric cancers: GPUs and machine learning techniques for variant detection [abstract]. In: Proceedings of the American Association for Cancer Research Annual Meeting 2021; 2021 Apr 10-15 and May 17-21. Philadelphia (PA): AACR; Cancer Res 2021;81(13_Suppl):Abstract nr 165.

To offer increased security and comfort, advanced driver-assistance systems (ADASs) should consider individual driving styles. Here, we present a system that learns a human's basic driving behavior and demonstrate its use as ADAS by issuing alerts when detecting inconsistent driving behavior. In contrast to much other work in this area, which is based on or obtained from simulation, our system is implemented as a multithreaded parallel central processing unit (CPU)/graphics processing unit (GPU) architecture in a real car and trained with real driving data to generate steering and acceleration control for road following. It also implements a method for detecting independently moving objects (IMOs) for spotting obstacles. Both learning and IMO detection algorithms are data driven and thus improve above the limitations of model-based approaches. The system's ability to imitate the teacher's behavior is analyzed on known and unknown streets, and results suggest its use for steering assistance but limit the use of the acceleration signal to curve negotiation. We propose that this ability to adapt to the driver can lead to better acceptance of ADAS, which is an important sales argument.

A comprehensive and effective parallel airborne synthetic aperture radar (SAR) processing system using the architecture of central processing units (CPU) and graphical processing units (GPU) is proposed first in this paper. By using the techniques of Compute Unified Device Architecture, the SAR processing system is much more efficient and robust, thereby enabling it to work with high efficiency. This paper focuses on the optimizations of motion compensation, subaperture chirp scaling algorithm, phase gradient autofocus (PGA), and even visualization with Open Source Computer Vision Library. Apart from this, it is also the first time the PGA has been run on the architecture of CPU and GPU. Experimental results show a speedup of ∼37 times compared with a nonoptimized CPU-based approach.

An embedded single media processor named MediaDSP3200 core fabricated in a six-layer metal 0.18um CMOS process which implemented the RISC instruction set, DSP data processing instruction set and single-instruction-multiple-data (SIMD) multimedia-enhanced instruction set is described. MediaDSP3200 fuses RISC architecture and DSP computation capability thoroughly, which achieves RISC fundamental, DSP extended and single instruction multiple data (SIMD) instruction set with various addressing modes in a unified pipeline stage architecture. These characteristics enhance system digital signal processing performance greatly. The test processor can achieve 32x32-bit multiply-accumulate (MAC) of 320 MOPS, with 16x16-bit MAC of 1280MOPS. The test processor dissipates 600mW at 1.8v, 320MHz. Also, the implementation was primarily standard cell logic design style. MediaDSP3200 targets diverse embedded application systems, which need both powerful processing/control capability and low-cost budget, e.g. set-top-boxes, video conferencing, DTV, etc. MediaDSP3200 instruction set architecture, addressing mode, pipeline design, SIMD feature, split-ALU and MAC are described in this paper. Finally, the performance benchmark based on H.264 and MPEG decoder algorithm are given in this paper.