X86-64 Core Architecture

This paper presents the design and implementation of a pipelined 9-bit RISC Processor. The various blocks include the Fetch, Decode, Execute and Store result to implement 4 stage pipelining. Harvard Architecture is used which has distinct program memory space and data memory space. The only load and store is used to communicate with data memory. RISC using pipeline makes CPI as 1 and improves speed of execution. Verilog Language is used for coding purpose. The proposed architecture is then simulated using Modelsim. Reduced Instruction Set Computers (RISCs) are now use for all type of computational tasks. In the area of scientific computing, RISC workstations are being increasingly used for compute task such as DSP, DIP etc. RISC concepts help to achieve given levels of performance at significantly lower cost than other systems. Pipelined RISC improves speed and cost effectiveness over the ease of hardware description language programming and conservation of memory and RISC based designs will continue to grow in speed and ability. The main features of RISC processor are the instruction set can be hardwired to speed instruction execution. In the present work, the design of a 4-bit data width Reduced Instruction Set Computer (RISC) processor is presented. It has a complete instruction set, program and data memories, general purpose registers and a simple Arithmetical Logical Unit (ALU) for basic operations. In this design, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate load and store instructions access memory. The architecture supports 8 instructions to support Arithmetic, Logical, Shifting, and load -store operations. Verilog HDL has evolved as a standard hardware description language. A hardware descriptive language is a language used to describe a digital system. HDL's allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology- independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits. More recently Verilog is used as an input for synthesis programs which will generate a gate-level description for the circuit. The simulator which is used for the language is Xilinx ISE and Modelsim. Verilog is capable of describing simple behaviour. Machine cycle instructions allow the processor to handle several instructions at the same time. The processor can work at a high clock frequency and thus yields higher speed. This paper is about design of a simple RISC processor and synthesizing it. The RISC architecture follows single-cycle instruction execution.

12 - The next generations

Many hardware-based defense schemes against speculative execution attacks use special mechanisms to protect instructions while speculative, and lift the mechanisms when the instructions turn non-speculative. In this paper, we observe that speculative instructions can sometimes become Speculation Invariant before turning non-speculative. Speculation invariance means that (i) whether the instruction will execute and (ii) the instruction's operands are not a function of speculative state. Hence, we propose to lift the protection mechanisms on these instructions early, when they become speculation invariant, and issue them without protection. As a result, we improve the performance of the defense schemes without changing their security properties. To exploit speculation invariance, we present the InvarSpec framework. InvarSpec includes a program analysis pass that identifies, for each relevant instruction i, the set of older instructions that are Safe for i-i.e., those that do not prevent i from becoming speculation invariant. At runtime, the InvarSpec micro-architecture loads this information and uses it to determine when speculative instructions can be issued without protection. InvarSpec is one of the first defense schemes for speculative execution that combines cooperative compiler and hardware mechanisms. Our evaluation shows that InvarSpec effectively reduces the execution overhead of hardware defense schemes. For example, on SPEC17, it reduces the average execution overhead of fence protections from 195.3% to 108.2%, of Delay-On-Miss from 39.5% to 24.4%, and of InvisiSpec from 15.4% to 10.9%.

As GPUs continue to grow in popularity for accelerating demanding applications, such as high-performance computing and machine learning, GPU architects need to deliver more powerful devices with updated instruction set architectures (ISAs) and new microarchitectural features. The introduction of the AMD RDNA architecture is one example where the GPU architecture was dramatically changed, modifying the underlying programming model, the core architecture, and the cache hierarchy. To date, no publicly-available simulator infrastructure can model the AMD RDNA GPU, preventing researchers from exploring new GPU designs based on the state-of-the-art RDNA architecture.

Hardware software co-design plays a crucial part in the embedded processor development especially with the current advancement of reconfigurable platforms. The reconfigurability features offered by platforms such as Field Programmable Gate Array (FPGA) has permitted the modification of the internal processor architecture with lower cost and higher performance. While the hardware architecture could be changed through various methods, the modifications need to be complemented with a compatible assembler that suits the amended architecture. This paper presents a two-pass assembler design technique that adapts to any instruction set architecture (ISA) modifications being applied on a reconfigurable processor. A Reduced Instruction Set Computer (RISC) processor core, which is described in Verilog Hardware Description Language (HDL), is used as the testing platform whereby its ISA is expanded to include new instruction sets. The assembler is developed based on two-pass approach and the assembling process would generate a coefficient file that is used as initialization files during the FPGA implementation of the processor core. The assemblers have been successfully developed with correct output format and verified during the FPGA implementation using Xilinx Spartan-3AN board.

The paper concerns a configurable soft core of the 8051 /spl mu/C implemented in VHDL. The main goal of efforts undertaken during design of the core was the full compatibility with the industrial standards 80C51 and 80C52 on the instruction and timing levels. It doesn't limit flexibility of the core's architecture, which can be easily optimized according to the current design constraints. The configuration capabilities of the core are grouped in a configuration package. That approach allows for separation from the indigenous part of the core, which remains untouched by a user and can be encoded in order to hide the VHDL code. Inside the configuration package there are several constants. Assigning values to them, a user has the opportunity to determine the core's structure (types of functional modules used in the core), RAM and ROM sizes, the instruction set, number of interrupted sources, number of execution cycles for division and multiplication, etc. The core is independent of the CPU peripheral modules (e.g. timer/counters, I/O ports, UART, etc.) due to a SFR bus. Peripherals are accessed by the use of special function registers. The upper half of available addresses of the internal RAM is just reserved for them. Hence the communication between the CPU and SFRs is carried out in the same way as in the case of memory cells. The core has been proven on silicon. It was applied in the smart pressure sensor chip and an 8031-compatible /spl mu/C. The compatibility with the industrial was checked on the logic verifier, where original 80C51 and 80C52 chips were applied during tests as references.

CYCLE TIME

80186 c compiler

Scandinavian firms choose DR personal s/w

Digital Signal Processors (DSPs) have shown the great strengths in digital signal processing algorithms such as digital filtering and Fourier analysis. This work is about an implementation for a specific computational unit based on the proposed RISC instruction set architecture (ISA) of 32-bit VLIW Fixed-point DSP processor core presented in our previous work. The computational unit is designed to be flexible for 32-bit/16-bit/8-bit data computations. The implementation is described from top-level to gate-level design and then it is verified to function correctly not only in Modelsim software but also on Altera Cyclone II (2C35) FPGA board.

Hardware and software co-verification from security perspective in SoC platforms

Multiplier-accumulator is a specific hardware unit that performs a common operation - computing the product of two numbers and adding that product to an accumulator. Especially, in digital signal processing applications which consist of a large number of convolution operations, the emergence of MAC unit contributes greatly to the high performance of the systems. This work is about an implementation for a specific MAC unit based on the proposed RISC instruction set architecture (ISA) of 32-bit VLIW Fixed-point DSP processor core presented in our previous work. The computational unit is designed to be flexible for 32-bit/16-bit/8-bit data computations. The implementation is verified to function correctly not only in Modelsim software but also on Altera Cyclone II (2C35) FPGA board.

The RISC-V instruction set architecture (ISA) is gaining wide adoption in domains such as IoT, embedded systems, and academic research due to its open-source, modular, and flexible design. A CPU core that is both efficient and easily verified is a basic prerequisite for such applications. In this work, we present the design and implementation of a Verilog HDL-based 32-bit single-cycle RISC-V processor that supports the RV32I instruction set. The processor integrates an Arithmetic Logic Unit (ALU), Register File, Control Unit, and Memory into a structured and modular datapath. Simulation and functional verification were performed using Eda Playground, where the correctness of instruction execution was confirmed through waveform analysis. The result of ALU operations is governed by the opcode and operands, where arithmetic operations (e.g., addition) perform A+B, logical operations (e.g., AND) perform <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{A} \wedge \mathrm{B}$</tex>, and memory instructions handle load/store between registers and memory. Status flags such as zero, carry, negative, and overflow are updated accordingly. The proposed design demonstrates improved efficiency through optimized control logic and reduced critical path delay, ensuring faster instruction execution in single-cycle operation. This processor serves as a foundational model for future enhancements such as pipelined or low-power architectures aimed at increasing performance and energy efficiency. The proposed modular top-level architectural synthesis approach improves scalability, verification simplicity, and enables seamless extension toward pipelined RISC-V architectures.

With increasing technology scaling and design complexity there are increasing threats from device and circuit failures. This is expected to worsen with post-CMOS devices. Current error-resilient solutions ensure reliability of circuits through protection mechanisms such as redundancy, error correction, and recovery. However, the costs of these solutions may be high, rendering them impractical. In contrast, error-tolerant solutions allow errors in the computation and are positioned to be suitable for error-tolerant applications such as media applications. For such programmable error-tolerant processors, the Instruction-Set-Architecture (ISA) no longer serves as a specification since it is acceptable for the processor to allow for errors during the execution of instructions. In this work, we address this specification gap by defining the basic requirements needed for an error-tolerant processor to provide acceptable results. Furthermore, we formally define properties that capture these requirements. Based on this, we propose the Partially Protected Uniprocessor (PPU), an error-tolerant processor that aims to meet these requirements with low-cost microarchitectural support. These protection mechanisms convert potentially fatal control errors to potentially tolerable data errors instead of ensuring instruction-level or byte-level correctness. The protection mechanisms in PPU protect the system against crashes, unresponsiveness, and external device corruption. In addition, they also provide support for achieving acceptable result quality. Additionally, we provide a methodology that formally proves the specification properties on PPU using model checking. This methodology uses models for the hardware and software that are integrated with the fault and recovery models. Finally, we experimentally demonstrate the results of model checking and the application-level quality of results for PPU.

In this paper the authors present a dual issue queued pipelined Java processor TRAJA 3.0. It can decode 162 instructions of the Java Virtual Machine (JVM)'s opcodes and it has a set of proprietary instructions. The pipeline has four instruction buffers and four decode queues to overcome the pipeline stalls on decoding the variable length instructions of the JVM. The processor also executes a restricted set of instruction folding and a restricted set of instruction reorder. In addition it has a caching scheme for the fast execution of the array instructions of the JVM.