應用於無線區域網路802.11a/b/g與60GHz之低雜訊放大器設計

ABSTRACTThis article presents two low noise amplifier (LNA) designs in 5.8 GHz using 0.18 μm CMOS technology, for dedicated short‐range communications (DSRC) applications. The source degenerate inductor is utilized for the cascode configuration with and without the mutual coupling from the gate inductor, to show the compromise between chip size and noise figure, where the mutual inductor reduces the chip area with a little increase of noise figure. To improve the receiver dynamic ranges of the two designed LNAs, the gain‐control function is added by the bias current bleeding at the common‐gate stage of the cascode configuration. The measured results accomplish 10.9 dB in gain and 3.6 dB in noise figure with −5 dBm of input 1 dB gain compression point (P1dB) for the design without mutual inductor, and 11.2 dB in gain and 4.4 dB in noise figure with −5 dBm input P1dB for the design with mutual inductor, while the chips occupy 0.42 mm2 and 0.36 mm2, respectively. These LNA designs can fulfill the requirements of DSRC applications. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2524–2529, 2015

This letter presents the design, performance, and analysis of four low-noise amplifier (LNA) monolithic microwave integrated circuits (MMICs) operating in W-band. Two LNA designs were fabricated in two variations of a 20-nm gate-length metal-oxide-semiconductor high-electron-mobility transistor (MOSHEMT) technology each. While for the first technology version the heterostructure is directly grown on the final gallium arsenide (GaAs) wafer, the second version uses direct wafer bonding to transfer the III-V heterostructure after the epitaxial growth to a silicon (Si) substrate. Based on the measured noise figure (NF) of the four MMICs over a comprehensive set of bias conditions, the impact of short-channel effects on the RF performance and possible improvements are analyzed. The first LNA covers an octave bandwidth with more than 15 dB of gain and an average NF (75-105 GHz) of 3.5 dB on a Si substrate. At 80 GHz, the second amplifier exhibits minimal NFs of 2.3 and 2.5 dB on GaAs and Si substrates, respectively. Compared to previously reported MOS- or Si-based technologies, the presented LNAs demonstrate state-of-the-art noise performance emphasizing the importance of electron confinement for highly scaled transistor technologies.

The abstract should summarize the contents of the paper in short terms, i.e. 150–250 words. In low noise amplifier (LNA) design, a prominent trade-off usually exist between noise-figure (NF) and gain. In this paper, impact of quality-factor (Q) of the inductors used in LNA design on the overall noise-figure and gain parameters are discussed. To understand the efficacy of the dependency of Q of inductors on NF, LNA with inductor available in UMC 0.18 μm Process Design Kit and LNA with parameterized-cell (pcell) based layout optimized high Q tapered inductors are realized, simulated and compared. Simulations study are carried out on a cascode source degenerated LNA. First, the LNA design is studied for different values of finite Q using library inductors. It is observed that the noise figure is reduced by about 65% (2.66 dB–1.61 dB) and gain is improved by about 30.2% (7.63–9.94) for the same design when Q of the inductors are increased from 10 to 30. Finally, the design is implemented using layout optimized high Q tapered inductors achieving lower noise figure of 1.2 dB with a better gain value of 16.45 and input return loss of −29.31 dB.

In this paper, a low-power ultra-wideband low noise amplifier (LNA) is presented. The combination of dual resonance network and current-bleeding technique offers high and flat voltage gain and low noise figure (NF), and also, the gain-controller resistor technique causes better control of voltage gain to achieve flatter gain. Furthermore, the CS–CD (Common-Source Common-Drain) current-reuse technique provides output return loss reduction and eliminates buffer stage in LNA design. It has been shown that using this scheme, noticeable improvement has been obtained in the frequency range of 2–11 GHz. This improvement consists of minimum noise figure value as 2.5 dB, the maximum value of 4.2 dB and average noise figure lower than 3 dB in a wide frequency range, from 4 to 10 GHz. The proposed LNA achieves the average voltage gain of 12.35 dB with a variation of 0.85 dB in the frequency range of 2–11 GHz. Input and output return losses are below − 10 dB and IIP3 of the proposed structure is − 3 dBm. The proposed LNA consumes 9.52 mW in 1-V supply voltage. Moreover, the size of the structure is 0.54 mm2 in TSMC 180-nm technology.

In this paper a low noise amplifier (LNA) with modified cascode structure in 45 GHz frequency band is presented. The LNA has been designed using TSMC 0.18 um RF-CMOS Technology The modified cascode structure is used to increase maximum stable gain (MSG), reduce noise figure and improve stability. In order to achieve wideband matching, band pass networks are used for input and output matching. This two stage LNA has 8 dB small signal gain and 4.8 dB noise figure in 45 GHz and the 3dB bandwidth is 20 GHz with insertion loss lower than −10 dB in all of the bandwidth. The supply voltage is 1.8 V and the consumed power is 11.2 mW. This LNA has better noise figure and bandwidth in comparison with the similar reported works.

This paper presents a design and optimization method for low noise amplifiers (LNAs), based on the minimization of the noise figure for a given power consumption. The LNA design is realized through the 0.18 mum CMOS process with the operating frequency at 2.14GHz. Simulation results show that the amplifier draws 5.36 mA from a given 1.8 V supply voltage while keeping the input/output impedance matched to 50 Omega. Furthermore, the circuit behaviors with 0.655 dB noise figure, gain of 16.64 dB, 1 dB compression point of about -12 dBm and IIP3 of 6 dBm.

Microwave integrated systems in silicon provide a low cost, low power and high yield solution for wideband data communication, radar, and many other applications. Phased-array systems are capable of steering the radiation beam by electronic means, emulating the behavior of a directional antenna. This dissertation is dedicated to presenting various techniques to implement microwave integrated phased-array receivers in silicon-based technologies in the context of three design examples. A 24-GHz 0.18-µm complementary metal oxide semiconductor (CMOS) front-end was demonstrated. The front-end consists of a low noise amplifier (LNA) and a mixer. The LNA utilizes a novel topology common-gate with resistive feedthrough to obtain low-noise performance. The entire front-end achieves a 7.7dB noise figure and a 27.5dB power gain. A fully integrated 8-element 24-GHz silicon germanium (SiGe) phased array receiver was implemented. The receiver uses two-step downconversion and local oscillator (LO) phase shifting with 4-bit resolution. The signal is combined at the 4.8-GHz intermediate frequency. The 16 phases of 19.2-GHz LO signal are generated with a voltage controlled oscillator (VCO) and symmetrically distributed to the phase selectors at all path. Appropriate phase sequence is applied to the phase distribution transmission lines to minimize mismatch. An integrated frequency synthesizer locks the 19.2-GHz VCO output to a 75-MHz external reference. Measured array patterns show a peak-to-null ratio of more than 20dB and a beam steering range covering all signal incident angles. An integrated 4-element 77-GHz SiGe wideband phased-array transceiver was implemented. Two-step conversion is used at both the receiver and the transmitter. A differential phase of 52 GHz is generated by the VCO and distributed to all RF paths at the transmitter and receiver. The phase shifting is performed at the LO ports of the RF mixers using continuous analog phase shifters. The quadrature signal of the second LO frequency is generated by dividing the VCO frequency by a factor of 2 using a cross-coupled injection-locked frequency divider. The signal combining is performed at IF with an active combining amplifier. The receiver achieves a 41dB gain at 80 GHz with 3 GHz of bandwidth. The 52-GHz-to-50MHz frequency divider chain obtains 7% locking range.

In this paper the design and implementation of a MMIC low noise amplifier (LNA) operating at 50–75 GHz band in 70 nm GaAs mHEMTs process is presented. The measured minimum noise figure (NF) is 2.7 dB and the maximum gain is 19.3 dB. The LNA is composed of three stages in cascaded common-source topology with more than 16.4 dB gain and less than 3 dB NF over the whole band. It is applicable in millimeter wave (mmWave) communications and measurement instruments.

In many designs, a low supply voltage is selected for efficient use of power. However, this often leads to low reverse‐isolation which is critical to the RF front–end circuits and particularly to the low‐noise amplifier (LNA). In this letter, a fully integrated differential low‐voltage CMOS LNA with high reverse‐isolation is presented. This LNA makes use of the single‐stage noncascode structure and the capacitive cross‐coupling (CCC) technique. The CCC technique has been utilized in many LNA designs. However, in all of the reported works using CCC, the CCC technique was mainly used to improve the noise figure (NF), not the reverse‐isolation. The poor reverse‐isolation problem in single‐stage noncascode structure has never been analyzed in the capacitive cross‐coupling cascaded low noise amplifier (CCCLNA). This work shows a novel analysis on the feedback self‐cancellation mechanism to improve the reverse‐isolation. Other analyses on input matching, gain and NF were also performed to show the feasibility of using CCC technique for the low‐voltage LNA as well as the advantages of the CCCLNA over the conventional common‐source and common‐gate (CG) LNA. The LNA consumes only 0.5 mW from 0.6 V supply voltage. It achieves a gain of 14 dB and a NF of 3.55 dB. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 54:374–379, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26542

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

This paper presents a high-gain, dual-band low noise amplifier (LNA) for 5G wireless systems, which supports simultaneous operation at 28 GHz and 38 GHz. The circuit consists of two cascode stages, and is implemented in a 22 nm FD-SOI CMOS technology. To realize the dual-band operation, dual-band matching networks based on transmission lines and capacitors were used. The presented LNA draws a current of 7.1 mA from a 1.6 V supply, which results in a total power consumption of 11.4 mW. The LNA provides a gain of 19.3 dB and 24 dB at 28 GHz and 38 GHz, respectively. At the input of the LNA a dual-band matching network was implemented to obtain a simultaneous noise and power matching at 28 GHz and 38 GHz. The measured noise figure at 28 GHz and 38 GHz is about 5 dB. The presented LNA compares well against previously reported designs by showing one of the highest gain and the lowest power consumption while still having the comparable performance in the other figures of merit. To the best knowledge of the authors, this is the first LNA using dual-band matching technique to support dual-band operation at 5G millimeter-wave bands.

A design methodology of Differential Design of CMOS low noise amplifier (LNA) with source degeneration for Bluetooth frequency is presented. The results show that the proposed topology is effective and can be used to achieve the minimum noise figure at all frequencies of interest. This LNA was realized in 0.18μm CMOS technology using Microwave Office Tool from AWR Inc. The measured noise figure is 2.066 dB and the gain is 20.29 dB.

This paper presents a 0.5-3.5GHz wideband CMOS low noise amplifier (LNA) for LTE application. The LNA design is based on a common source (CS) cascade amplifier with resistive feedback that is used to do input matching and reduce the noise figure. Source follower and LC series resonances are used to do output matching. The LNA achieves the gain of 17dB ∼ 22dB, a noise figure (NF) of 2.23 ∼ 2.68 dB at frequency from 0.5 to 3.5 GHz, The DC power consumption is 32.8mW at 1.8 V supply voltage. The LNA is fabricated with TSMC 0.18-µm CMOS process. The chip size is 0.6mm*0.8mm.

This paper presents a 0.6-6.2 GHz wideband CMOS low noise amplifier (LNA) for multi-band application. The LNA design is based on a common source (CS) cascade amplifier with resistive feedback, gate inductive peaking, and source degeneration inductive topologies to realize the matching networks for broadband operation. The authors also derived the formula of the input and output impedances those help to select proper values of biasing and matching elements. The LNA achieves a peak gain S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> of 11.61 dB, a noise figure (NF) of 5.28 to 5.82 dB at frequency from 0.6 to 6.2 GHz, and an input third-intercept point (IIP3) of -2.55 dBm at 2.5 GHz under DC power of 8.45 mW from a 1.5 V supply voltage. The figure-of-merit (FOM) for wideband LNA is up to 0.51 at 2.5 GHz. The LNA is fabricated in tsmc™ 0.18-μm RF CMOS technology with a chip area of 0.8 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 20 GHz sub-1 V low noise amplifier and a resistive mixer are designed and fabricated in 90 nm CMOS technology. The LNA achieves a good linearity along with a moderate gain and noise figure. For instance, at 0.9 V supply voltage, 8.8 dB of gain and 5.2 dB of noise figure, as well as 7.0 dBm of IIP3 are obtained. This LNA can work properly even at a supply voltage as low as 0.66 V. It achieves 8.0 dB of gain, 5.3 dB of noise figure, and 3.8 dBm of III3. The DC consumption is 16.8 mW and 11 mW for a supply voltage of 0.9 V and 0.66 V, respectively. This is the first report of a high frequency CMOS LNA operating at such low supply voltage and low DC power dissipation. Moreover, a 20 GHz resistive passive mixer is presented, exhibiting a high IIP3 of 19 dBm, a moderate conversion loss of 7.6 dB, and a low noise figure of 4.35 dB. It consumes no DC power. Thus, these two circuits are suitable to be applied in a high frequency CMOS front-end operating with sub-1 V supply.