A 0.6‐V high reverse‐isolation through feedback self‐cancellation for single‐stage noncascode CMOS LNA

This paper presents a 0.5-3.5GHz wideband CMOS low noise amplifier (LNA) for LTE application. The LNA design is based on a common source (CS) cascade amplifier with resistive feedback that is used to do input matching and reduce the noise figure. Source follower and LC series resonances are used to do output matching. The LNA achieves the gain of 17dB ∼ 22dB, a noise figure (NF) of 2.23 ∼ 2.68 dB at frequency from 0.5 to 3.5 GHz, The DC power consumption is 32.8mW at 1.8 V supply voltage. The LNA is fabricated with TSMC 0.18-µm CMOS process. The chip size is 0.6mm*0.8mm.

The wireless communication industry is currently experiencing tremendous growth. In responding to the demand for a low-cost but high performance wireless front-end, many intensive researches on CMOS radio-frequency (RF) front-end circuits have been carried out. The ultimate goal is to minimize the trade-off between high performance and low-cost, low power consumption design. Low noise amplifier (LNA) is typically the first stage of a receiver. Its performance greatly affects the overall receiver performance. In this thesis, four LNAs are proposed. They are designed for the IEEE 802.15.4 standard in the 2.4 GHz ISM band. The first three LNAs are optimized for low NF and low power. An application of this type of LNA is to be used as the amplification stage before the active mixer in the receiver chain . Active mixer provides active gain while consuming some dc power. Therefore the LNA's gain requirement can be relaxed. But its power consumption needs to be low to compensate for the power consumption from the active mixer. With a relaxed gain, the LNA should have good NF to avoid degrading the overall receiver NF. The fourth LNA is optimized for high gain. This optimization is useful in the receiver system where passive mixer is used for frequency conversion. Passive mixer consumes no dc power while having some conversion loss. Therefore, high LNA gain is required in this type of system.There are four important contributions in this research. Firstly, and LNA (LNA1) that combining the merits of the inductive source degeneration common-source LNA (L-CSLNA) and the common-gate LNA (CGLNA) is introduced. The proposed LNA1 is a fully differential gm-boosting CGLNA with series inductor input matching network that improves the NF. The circuit's input matching, NF and gain have been derived to verify the design methodology. The LNA was designed and fabricated using 0.18 μm CMOS technology. It consumes only 0.98 mA from 1.0 V power supply and achieves a measured gain of 15 dB and NF of 5 dB. The series inductor input matching CGLNA is attractive for low-power fully integrated applications in CMOS technologies. Even though the high NF problem of the CGLNA has been addressed in the proposed LNA1, we wish to further reduce the NF to achieve better trade-off between NF and power consumption. LNA2 was designed with a simple but effective noise-reducing technique. An inductor was added in parallel to the input transistor to reduce the noise from both the cascode and the input transistor. The LNA's input matching, NF and gain have been derived to verify the design methodology. The LNA achieves a measured gain of 14.8 dB, NF of 4.5 dB and IIP3 of -5.7dBm respectively. It consumes only 0.95 mW from a 1.0 V supply voltage.

The abstract should summarize the contents of the paper in short terms, i.e. 150–250 words. In low noise amplifier (LNA) design, a prominent trade-off usually exist between noise-figure (NF) and gain. In this paper, impact of quality-factor (Q) of the inductors used in LNA design on the overall noise-figure and gain parameters are discussed. To understand the efficacy of the dependency of Q of inductors on NF, LNA with inductor available in UMC 0.18 μm Process Design Kit and LNA with parameterized-cell (pcell) based layout optimized high Q tapered inductors are realized, simulated and compared. Simulations study are carried out on a cascode source degenerated LNA. First, the LNA design is studied for different values of finite Q using library inductors. It is observed that the noise figure is reduced by about 65% (2.66 dB–1.61 dB) and gain is improved by about 30.2% (7.63–9.94) for the same design when Q of the inductors are increased from 10 to 30. Finally, the design is implemented using layout optimized high Q tapered inductors achieving lower noise figure of 1.2 dB with a better gain value of 16.45 and input return loss of −29.31 dB.

This thesis focuses on the low noise amplifier design of RF receivers for WLAN 802.11a/b/g dual-band and 60GHz applications, in which we cover the topics including introduction to bands and applications, literature review, circuit designs, chips’ measurement results and discussions of the results. There are four chapters to discourse on the basis of low noise amplifier design, and circuit implementations. In Chapter 1, we introduce the wireless RF system, IEEE 802.11 bands, and optical transmission and wireless communications systems development. In Chapter 2, important parameters of LNA are described, including introduction, impedance matching theory, matching network design, noise figure, linearity, and stability. Chapter 3 is focused on the design of a sub 1V CMOS low noise amplifier for dual-band application. This chapter starts from studying three basic topologies for LNA, including their matching design and noise ability. Then we use low voltage characteristics of the folded cascode circuit to design a low power consumption circuit for 2.4GHz/5GHz dual band application. The chip is implemented using TSMC 0.18um CMOS process technology. The measured peak gains are 13.9 dB and 9.6dB at frequencies 2.4GHz and 5GHz, respectively. The measured noise figures are 3.9 dB and 4.7 dB, respectively, for both bands. The power consumption of the circuit is 5.5mW under 1V supply voltage. The subject of Chapter 4 is the 60GHz low noise amplifier design using GaAs process technology, and probing the technology behavior of the GaAs process and its applications. This chip is fabricated using WIN 0.15um pHEMT process. The measured peak gain of this 60GHz GaAs LNA is 11dB at 55.7GHz, and the measured noise figure is 4.8dB. The power consumption of the circuit is 26.6mW under 1.8V supply voltage. In Chapter 5, a 60GHz LNA using TSMC 90nm CMOS process technology is presented. The measurement results show a 6.57 dB gain and a 7.4 dB noise figure at 59GHz. The power consumption of the circuit is 9.4mW under 1.2V supply voltage.

In this paper a low noise amplifier (LNA) with modified cascode structure in 45 GHz frequency band is presented. The LNA has been designed using TSMC 0.18 um RF-CMOS Technology The modified cascode structure is used to increase maximum stable gain (MSG), reduce noise figure and improve stability. In order to achieve wideband matching, band pass networks are used for input and output matching. This two stage LNA has 8 dB small signal gain and 4.8 dB noise figure in 45 GHz and the 3dB bandwidth is 20 GHz with insertion loss lower than −10 dB in all of the bandwidth. The supply voltage is 1.8 V and the consumed power is 11.2 mW. This LNA has better noise figure and bandwidth in comparison with the similar reported works.

This paper presents a 0.6-6.2 GHz wideband CMOS low noise amplifier (LNA) for multi-band application. The LNA design is based on a common source (CS) cascade amplifier with resistive feedback, gate inductive peaking, and source degeneration inductive topologies to realize the matching networks for broadband operation. The authors also derived the formula of the input and output impedances those help to select proper values of biasing and matching elements. The LNA achieves a peak gain S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> of 11.61 dB, a noise figure (NF) of 5.28 to 5.82 dB at frequency from 0.6 to 6.2 GHz, and an input third-intercept point (IIP3) of -2.55 dBm at 2.5 GHz under DC power of 8.45 mW from a 1.5 V supply voltage. The figure-of-merit (FOM) for wideband LNA is up to 0.51 at 2.5 GHz. The LNA is fabricated in tsmc™ 0.18-μm RF CMOS technology with a chip area of 0.8 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

ABSTRACTThis article presents two low noise amplifier (LNA) designs in 5.8 GHz using 0.18 μm CMOS technology, for dedicated short‐range communications (DSRC) applications. The source degenerate inductor is utilized for the cascode configuration with and without the mutual coupling from the gate inductor, to show the compromise between chip size and noise figure, where the mutual inductor reduces the chip area with a little increase of noise figure. To improve the receiver dynamic ranges of the two designed LNAs, the gain‐control function is added by the bias current bleeding at the common‐gate stage of the cascode configuration. The measured results accomplish 10.9 dB in gain and 3.6 dB in noise figure with −5 dBm of input 1 dB gain compression point (P1dB) for the design without mutual inductor, and 11.2 dB in gain and 4.4 dB in noise figure with −5 dBm input P1dB for the design with mutual inductor, while the chips occupy 0.42 mm2 and 0.36 mm2, respectively. These LNA designs can fulfill the requirements of DSRC applications. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2524–2529, 2015

This paper investigates the low-power potential of SiGe HBTs in V-band low noise amplifier(LNA) designs. An LNA consisting of a single-stage cascode circuit has been designed in the IHP 130nm SiGe technology. Different biasing conditions of the transistors have been investigated to find the optimum for low-power, low-noise and high-gain operation. The current density has been chosen to achieve a proper balance between the gain and noise performance. To minimize the DC power, the supply voltage has been chosen to be the lowest required to ensure sufficient gain and noise figure. The device dimensions of the LNA have been determined to enable a low-loss broadband input matching by solely using a single series inductor. The designed LNA achieves a minimum noise figure of 2.4dB under a nominal supply voltage of 0.6V. The noise figure on average is 2.8dB from 54GHz to 67GHz. At the nominal supply voltage, the LNA consumes only 1.4mW DC power and provides a gain of around 14dB and a bandwidth of 7.3GHz.

In this paper, A CMOS low noise amplifier (LNA) with an integrated notch feedback for interferer cancellation is presented. The proposed LNA adopts the integrated tunable notch feedback stage to cancel interferer signals at the input of the LNA, which eliminates the need of an off-chip filter. To improve the quality factor of the LC resonators, Q-enhancement circuit is used in the notch feedback stage. The proposed LNA is designed in a 0.13 μm CMOS technology. The LNA with the integrated notch feedback achieves an interferer rejection of 21.6 dB with a interferer at 80 MHz offset. A noise figure is 6.1 dB at 1.9 GHz center frequency, an input-referred third-order intercept point is - 16.7 dBm and the LNA consumes a current of 37.8 mA from a 1.2 V supply voltage when the notch feedback stage is on.

In this paper, a low-power ultra-wideband low noise amplifier (LNA) is presented. The combination of dual resonance network and current-bleeding technique offers high and flat voltage gain and low noise figure (NF), and also, the gain-controller resistor technique causes better control of voltage gain to achieve flatter gain. Furthermore, the CS–CD (Common-Source Common-Drain) current-reuse technique provides output return loss reduction and eliminates buffer stage in LNA design. It has been shown that using this scheme, noticeable improvement has been obtained in the frequency range of 2–11 GHz. This improvement consists of minimum noise figure value as 2.5 dB, the maximum value of 4.2 dB and average noise figure lower than 3 dB in a wide frequency range, from 4 to 10 GHz. The proposed LNA achieves the average voltage gain of 12.35 dB with a variation of 0.85 dB in the frequency range of 2–11 GHz. Input and output return losses are below − 10 dB and IIP3 of the proposed structure is − 3 dBm. The proposed LNA consumes 9.52 mW in 1-V supply voltage. Moreover, the size of the structure is 0.54 mm2 in TSMC 180-nm technology.

A 0.5---2.5 GHz ultra low power differential resistive feedback common gate low noise amplifier (RFCGLNA) without the use of inductor is presented. The proposed RFCGLNA adopts the NMOS and PMOS complementary topology to reduce the power consumption by half. Based on common-gate topology, the proposed RFCGLNA employs capacitive cross-coupling (CCC) and resistive feedback techniques. The CCC technique can further reduce the power consumption by half. The resistive feedback technique can constrain the common mode voltages of the proposed RFCGLNA and meanwhile, improve the third-order input intercept point (IIP3). The DC path is supplied by the current source transistor which forms a positive feedback loop to improve the gain at low frequency. Implemented with 65 nm standard complementary metal oxide semiconductor (CMOS) technology, the measured performance achieves 15 dB gain with S11 < ?10 dB in the 0.5---2.5 GHz band. The noise figure (NF) is 3.9---5.0 dB and the IIP3 is 3.1---3.6 dBm. The power consumption is only 910 uW.

&lt;p class="Abstract"&gt;&lt;span&gt;The demand of low noise amplifier (LNA) has been rising in today’s communication system. LNA is the basic building circuit of the receiver section satellite. The design concept demonstrates the design trade off with NF, gain, power consumption. This paper reports on with analysis of wideband LNA. This paper shows the schematic of LNA by using Darlington pair amplifier. This LNA has been fabricated on 90nm CMOS process. This paper is focused on to make comparison of three stage and single stage LNA. Here, the phase mismatch between these patameters is quantitavely analyzed to study the effect on gain and noise figure (NF). In this paper, single stage LNA has shown the 23 dB measured gain, while the three stages LNA has demonstrated 29 dB measured gain. Here, LNA designed using darlington pair shows low NF of 3.3-4.8 dB, which comparable to other reported single stage LNA designs and appreciably low compared to the three stages LNA. Hence, findings from this paper suggest the use of single stage LNA designed using Darlington pair in transceiver satellite applications.&lt;/span&gt;&lt;/p&gt;

This paper presents an ultra-wideband (UWB) CMOS low noise amplifier (LNA) that combines a narrowband LNA with resistive shunt- feedback. A new feedback topology is proposed based on the analysis of the influences of feedback scheme on the performances of the LNA. The noise figure (NF) and the power gain, compared with those of a previous shunt-feedback LNA topology, are decreased by 0.8 dB and increased by 2.5 dB respectively while other performances have little change. Designed in a 0.18- mum CMOS technology, the LNA shows a minimum NF of 2.2 dB, a power gain of 11 dB with plusmn0.6 dB variation, and an input return loss of more than 9 dB over the 3.1-5 GHz UWB band.

A low-power, high-gain Silicon on Insulator (SOI) CMOS low noise amplifier (LNA) for use as the first stage of a subsampling receiver for space application at UHF frequency is proposed for the first time. The simulated results of +80 dB available gain and 2.1-dB noise figure (NF) with very low power consumption is reported and makes it suitable for subsampling mixer with Track and Hold (T/H) circuit. The LNA contains both tuned and inductorless amplifier stages. The first stage utilizes resonant tank with on-chip capacitors and improved-Q spiral inductors. The following stage is composed of five inductorless amplifiers designed to achieve the high-gain. Both stages apply fully differential architecture with cascoded transistors to achieve high-gain, low-power at high frequencies with reasonable reverse isolation. This is the first high-gain LNA design using SOI CMOS technology.

Low-noise amplifiers (LNAs) are one of the important building blocks of wireless receivers. LNA design parameters such as gain, noise figure, linearity, input matching, and stability are important metrics and typically affect the overall performance of the receiver. The strong trade-offs among these design parameters often necessitate several design iterations. While many of these trade-offs are due to the nature of the circuit and are inevitable, it is desirable to decouple the effects of each parameter on the others. In this work, body biasing is introduced as a technique to enhance the linearity, to improve the noise figure and to provide gain variation. These techniques are presented in the context of a three-stage LNA. By applying body biasing in each stage, noise figure, gain variation and linearity of the overall amplifier are adjusted almost independently, i.e., with minimal interrelation among these design parameters. As a proof-of-concept, a prototype 4.4-GHz LNA is designed and fabricated in a 0.13- μm CMOS technology. The LNA achieves a minimum noise figure of 3.8 dB, maximum gain of 20.2 dB, and a maximum IIP3 of -14 dBm while consuming 3.6 mW from a 1.2 V supply.