A 0.5–2.5 GHz 910 uW complementary LNA employing positive–negative feedback

This paper proposes a common gate down conversion mixer with Capacitor Cross Coupling (CCC) technique designed for UHF 900 MHz RFID reader receiver chain. In this work, the common gate (CG) topology in the input stage has been applied to achieve high saturation level to expand voltage swing range. But due to the disadvantage of CG topology, it has poor gain and noise performance. Consequently, the technique of capacitor cross-coupling (CCC) has been adopted to improve conversion gain and noise figure (NF) based on CG topology. The mixer performance with and without the technique of CCC is compared. The operating frequency is 900MHz in UHF band. This circuit has been simulated in cadence Spectre environment and implemented in Tower Jazz 018 CMOS process under 3.3V supply. The simulation results show the improvement on conversion gain and Noise Figure (NF) by 4.5dB and 1.3dB, respectively. And the variations of CCC, from 0.2pF to 4pF, are implemented to get knowledge of performance varying dependent on CC capacitance.

In many designs, a low supply voltage is selected for efficient use of power. However, this often leads to low reverse‐isolation which is critical to the RF front–end circuits and particularly to the low‐noise amplifier (LNA). In this letter, a fully integrated differential low‐voltage CMOS LNA with high reverse‐isolation is presented. This LNA makes use of the single‐stage noncascode structure and the capacitive cross‐coupling (CCC) technique. The CCC technique has been utilized in many LNA designs. However, in all of the reported works using CCC, the CCC technique was mainly used to improve the noise figure (NF), not the reverse‐isolation. The poor reverse‐isolation problem in single‐stage noncascode structure has never been analyzed in the capacitive cross‐coupling cascaded low noise amplifier (CCCLNA). This work shows a novel analysis on the feedback self‐cancellation mechanism to improve the reverse‐isolation. Other analyses on input matching, gain and NF were also performed to show the feasibility of using CCC technique for the low‐voltage LNA as well as the advantages of the CCCLNA over the conventional common‐source and common‐gate (CG) LNA. The LNA consumes only 0.5 mW from 0.6 V supply voltage. It achieves a gain of 14 dB and a NF of 3.55 dB. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 54:374–379, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26542

A novel wide tuning range variable gain differential low-noise amplifier (LNA) with digital assisted automatic tuning loop for multi-mode receiver is proposed in this paper. Common gate LNA with cross-coupled capacitor (CCC) and positive feedback is applied for tuning flexibility and high gain, low noise performance. Digital assisted automatic tuning mechanism reuses the output load inductor and capacitor tank to configure an auxiliary oscillator while tuning, and re-configures it back to narrowband LNA, without extra chip area and power consumption. A testchip is fabricated in 0.13μm CMOS. Measurement results show an LNA performance of 8~26dB variable voltage gain, 2dB NF, -5.5dBm IIP3 and S11<;-10dB. The digital assisted automatic frequency tuning range covers 1.9-2.6GHz with 1% tuning error. The circuit consumes 8mA with 1.2V power supply and the core layout size is 0.35mm×0.55mm.

Scalable nano-bioprobes with sub-cellular resolution for cell detection

ABSTRACTThe rapid growth of scaling and integration of nano-scale digital circuits is hardly tracked by the analog circuits which require additional passive components for fabrication. Mixed-signal Complementary Metal Oxide Semiconductor (CMOS) technologies are released with some delays after digital CMOS technologies, due to the issues related to integration of analog components. This urges the designers to consider using the same digital CMOS technology for integration of advanced analog circuits like continuous-time filters. As such, this article presents an area-efficient Gm–C filter made from MOS devices only. Instead of classical metal–insulator–metal capacitors, the proposed filter exploits the available compact-size MOS devices as capacitor. This modification makes the filter design compatible to any low-cost digital CMOS process. Besides, the 3-dB cut-off frequency of the filter can now be changed by varying the size of MOS capacitors. The effectiveness of the new design approach is validated through simulation of a fifth-order elliptic low-pass filter with a cut-off frequency of 1 MHz in 90-nm CMOS technology. The new filter dissipates around 115 µW from a 1.0 V power supply, and the sensitivity of its cut-off frequency is kept as low as 6% over various process and temperature corners.

In today’s technology, optical networking plays a vital role in reducing data losses, thereby providing higher data rates between the transreceivers. The very large scale integration circuits in the modulator–demodulator (MODEM) usually fabricated using complementary metal oxide semiconductor (CMOS) technology have serious scaling limitations; hence, device scaling beyond 65 nm technology becomes highly challenging. Quantum-dot cellular automata (QCA) is one of the most promising nanotechnologies that enable areas of smaller size, i.e. 60% less design area than the CMOS technology, with capability to produce high speed by taking less cycles compared with the other CMOS designs to reduce scaling issues. The QCA-based designs are considered as the best alternative solutions to the transistor-based (CMOS) designs. This paper deals with the implementation of the logic gates NOT, AND, OR, NAND, NOR, XOR and XNOR using both CMOS and QCA technologies, while the QCA allows more possible design structures for each logic gate to enable optimization of the area. Finally, the proposed QCA-based logic gate design and CMOS-based designs are compared in terms of the design area, cell count and the speed of the designs. QCA designer 2.0.3 and virtuoso CADENCE Computer-Aided Design tools are used for carrying out the work.

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. C/sub w/=0.2 pF) delay per stage of 280 ps achieved (W/sub eff//L/sub eff/=15 mu m/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m), a CMOS stage delay of 38 ps for unloaded inverter ring oscillators and 185 ps for loaded NAND are demonstrated. A reduced operating voltage in the range of 2.2-2.5 V is chosen to optimize performance without compromising reliability. Shallow junctions with abrupt profiles are used to minimize device series resistance as well as gate-to-source/drain (S/D) overlap capacitance. Dural poly (n/sup +/ and p/sup +/) gates are used to avoid buried-channel operation pFETs, resulting in superior short-channel characteristics. Poly and S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new pixel is designed with the capability of imaging and energy harvesting for the retinal prosthesis implant in 0.18 µm standard Complementary Metal Oxide Semiconductor technology. The pixel conversion gain and dynamic range, are 2.05 $$\upmu{\text{V}}/{\text{e}}^{ - }$$ and 63.2 dB. The power consumption 53.12 pW per pixel while energy harvesting performance is 3.87 nW in 60 klx of illuminance per pixel. These results have been obtained using post layout simulation. In the proposed pixel structure, the high power production capability in energy harvesting mode covers the demanded energy by using all available p-n junction photo generated currents.

An on-chip transformer, with two inductors magnetically coupled, provides input single-to-differential conversion (passive balun) for a differential low-noise amplifier (LNA), but significantly influences its input impedance and noise performance. We derive the analytical expressions for the performances of differential inductively-degenerated common-source (CS) LNA and cross-coupled common-gate (CG) LNA with on-chip transformers to present their design considerations. The derived expressions provide the minimum requirement for the quality factor of the inductor and the optimum inductance for the minimum noise figure (NF) of the LNA. Both the LNAs with inter-winding symmetric octagonal transformers are designed for Bluetooth Low Energy (BLE) receivers with a 65-nm CMOS process. Simulations show that the differential CS and CG LNAs achieve |S 21 | of 20.4 dB and 20.9 dB, and NF of 5.18 dB and 4.55 dB at 2.45 GHz, respectively, with a power consumption of 2.8 mW from a 0.7-V supply. The CG LNA can achieve a higher gain and lower NF than the CS one. The presented analysis and design considerations significantly reduce the design efforts to differential LNAs with on-chip transformers.

A capacitor cross-coupled (CCC) wideband common-gate low-noise amplifier (CGLNA) with improved linearity and frequency response is presented. A novel differential active inductor (AI) is designed to improve the in-band gain flatness and high-frequency gain using the gate-inductive gain-peaking technique. The AI prevents the small-signal current flowing to the ground through the gate–drain capacitors. The CCC technique improves noise performance and saves power. However, it will also increase nonlinear distortions due to the boosted signal amplitude. To overcome the CCC-induced linearity deterioration, the derivative superposition technique is employed by using two parallel input transistors biased at different regions. The measurement results of the fabricated prototype in a 0.18- $\mu\text{m}$ CMOS process show that the voltage gain, the minimum noise figure, and the third-order intercept point are 16.9 dB, 2.5 dB, and 5.5 dBm, respectively, within the 3-dB bandwidth from 100 MHz to 1.45 GHz. The CGLNA consumes 9.3 mW from a 1.8-V supply and the active area is $0.29\times 0.26 \text{mm}^{2}$ .

Traditional logical equivalence checking (LEC), which plays a major role in the entire chip design process, faces challenges of meeting the requirements demanded by the many emerging technologies that are based on logic models different from the standard complementary metal oxide semiconductor (CMOS). In this article, we propose an LEC framework to be employed in the verification process of superconducting electronics (SCE). Our LEC framework is compatible with the existing CMOS technologies and can also check features and capabilities that are unique to SCE. For instance, the performance of nonresistively biased single-flux quantum (SFQ) circuits benefits from ultradeep pipelining, and verification of such circuits requires new models and algorithms. We, therefore, present the multicycle input dependency circuit model which is a novel model representation of design to explicitly capture the dependency of primary outputs of the circuit on sequences of internal signals and inputs. Embedding the proposed circuit model and several structural checking modules, the process of verification can be independent of the underlying technology and signaling. We benchmark the proposed framework on postsynthesis SFQ and 4-phase adiabatic quantum flux parametron netlists. Results show a comparative verification time of SFQ circuit benchmark, including 16-bit integer divider and ISCAS’85 circuits with respect to the ABC tool for similar CMOS circuits.

Decimal arithmetic is gaining more attention by researchers due to their importance in many human-centric applications. Hardware implementations of decimal arithmetic are preferable over their software counterparts as the former leads in performance especially when it comes to real-time applications. Decimal addition is a main decimal operation as most of the other decimal operation can be implemented using decimal addition. Complementary Metal Oxide Semiconductor (CMOS) technology has the advantage of reducing the average power consumption and the propagation delay in digital systems. Decimal adders can be designed as a ripple carry addition (RCA) structure or as a carry look-ahead addition (CLA) structure with the latter being faster with extra hardware cost. This work proposes two CMOS-based carry look-ahead decimal adders (CLDAs) that can be used within any decimal arithmetic unit. Operands of 1-digit size, 2-digit size, 3-digit size, and 4-digit size are investigated. The Boolean logic for each of the proposed CLDAs is developed and the CMOS realization is provided. The circuit of each of the proposed CLDAs is simulated with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$45~nm$ </tex-math></inline-formula> technology library using the LT-SPICE spice simulation tool. The simulation shows promising results in terms of speed, power, and power delay product (PDP).

In this article, a three-stage and five-stage voltage-controlled oscillator (VCO) using current starved configuration has been proposed. Among the two, only a three-stage VCO gives the required bandwidth of 5 GHz. Current starved VCO is designed using complementary metal oxide semiconductor (CMOS) technology. The oscillating output frequency bandwidth (2–7 GHz) is considered as the main objective for the proposed circuit. The proposed three-stage VCO circuit uses low supply voltage of 1 V, low power of 29.93 uW. Transient analysis and periodic steady state (PSS) analysis are performed, and after simulation, a wide frequency bandwidth of 5 GHz was obtained. The phase noise for the three-stage VCO at 1 GHz is −132 dBc/Hz. The circuit has been designed in Cadence Virtuso using gpdk 45 nm CMOS technology with supply voltage of 1 V.

Although sorting networks have extensively been reported in literature (Batcher, 1962), there are a few references that cover a detailed explanation about their VLSI (Very Large Scale of Integration) realization in CMOS (Complementary Metal-Oxide-Semiconductor) technology (Turan et al., 2003). From an algorithmic point of view, a sorting network is defined as a sequence of compare and interchange operations depending only on the number of elements to be sorted. From a hardware perspective, sorting networks can be visualized as combinatorial circuits where a set of denoted compare-swap (CS) circuits can be connected in accordance to a specific network topology (Knuth, 1997). In this chapter, the design of sorting networks in CMOS technology with applicability to VLSI design is approached at block, transistor, and layout levels. Special attention has been placed to show the hierarchical structure observed in sorting schemes where the so called CS circuit constitutes the fundamental standard cell. The CS circuit is characterized through SPICE simulation making a particular emphasis in the silicon area and delay time parameters. In order to illustrate the inclusion of sorting networks into specific applications, like signal processing and nonlinear function evaluation, two already reported examples of integrated circuit designs are provided (Agustin et al., 2011; Jimenez et al., 2011).

We implanted high energy boron to create a heavily doped ground plane in Cz wafers in order to replace p/p/sup +/ episubstrates in deep submicron complementary metal-oxide semiconductor (CMOS) technology. Devices manufactured on Cz wafers with a 1.5 or 1.6 MeV, 1/spl times/10/sup 15/ cm/sup -2/ boron implanted ground plane have superior latch-up immunity as compared to devices on epiwafers. Improvements in latch-up suppression were observed for all isolation spacings. Diode leakage was lower in high dose buried-layer substrates than in episubstrates, while gate oxide integrity was equivalent. For the first time, buried layer substrates have been shown to duplicate or exceed the performance of episilicon simultaneously for all relevant CMOS transistor and circuit parameters.