Scalable nano-bioprobes with sub-cellular resolution for cell detection

A 0.5---2.5 GHz ultra low power differential resistive feedback common gate low noise amplifier (RFCGLNA) without the use of inductor is presented. The proposed RFCGLNA adopts the NMOS and PMOS complementary topology to reduce the power consumption by half. Based on common-gate topology, the proposed RFCGLNA employs capacitive cross-coupling (CCC) and resistive feedback techniques. The CCC technique can further reduce the power consumption by half. The resistive feedback technique can constrain the common mode voltages of the proposed RFCGLNA and meanwhile, improve the third-order input intercept point (IIP3). The DC path is supplied by the current source transistor which forms a positive feedback loop to improve the gain at low frequency. Implemented with 65 nm standard complementary metal oxide semiconductor (CMOS) technology, the measured performance achieves 15 dB gain with S11 < ?10 dB in the 0.5---2.5 GHz band. The noise figure (NF) is 3.9---5.0 dB and the IIP3 is 3.1---3.6 dBm. The power consumption is only 910 uW.

A new pixel is designed with the capability of imaging and energy harvesting for the retinal prosthesis implant in 0.18 µm standard Complementary Metal Oxide Semiconductor technology. The pixel conversion gain and dynamic range, are 2.05 $$\upmu{\text{V}}/{\text{e}}^{ - }$$ and 63.2 dB. The power consumption 53.12 pW per pixel while energy harvesting performance is 3.87 nW in 60 klx of illuminance per pixel. These results have been obtained using post layout simulation. In the proposed pixel structure, the high power production capability in energy harvesting mode covers the demanded energy by using all available p-n junction photo generated currents.

ABSTRACTThe rapid growth of scaling and integration of nano-scale digital circuits is hardly tracked by the analog circuits which require additional passive components for fabrication. Mixed-signal Complementary Metal Oxide Semiconductor (CMOS) technologies are released with some delays after digital CMOS technologies, due to the issues related to integration of analog components. This urges the designers to consider using the same digital CMOS technology for integration of advanced analog circuits like continuous-time filters. As such, this article presents an area-efficient Gm–C filter made from MOS devices only. Instead of classical metal–insulator–metal capacitors, the proposed filter exploits the available compact-size MOS devices as capacitor. This modification makes the filter design compatible to any low-cost digital CMOS process. Besides, the 3-dB cut-off frequency of the filter can now be changed by varying the size of MOS capacitors. The effectiveness of the new design approach is validated through simulation of a fifth-order elliptic low-pass filter with a cut-off frequency of 1 MHz in 90-nm CMOS technology. The new filter dissipates around 115 µW from a 1.0 V power supply, and the sensitivity of its cut-off frequency is kept as low as 6% over various process and temperature corners.

In today’s technology, optical networking plays a vital role in reducing data losses, thereby providing higher data rates between the transreceivers. The very large scale integration circuits in the modulator–demodulator (MODEM) usually fabricated using complementary metal oxide semiconductor (CMOS) technology have serious scaling limitations; hence, device scaling beyond 65 nm technology becomes highly challenging. Quantum-dot cellular automata (QCA) is one of the most promising nanotechnologies that enable areas of smaller size, i.e. 60% less design area than the CMOS technology, with capability to produce high speed by taking less cycles compared with the other CMOS designs to reduce scaling issues. The QCA-based designs are considered as the best alternative solutions to the transistor-based (CMOS) designs. This paper deals with the implementation of the logic gates NOT, AND, OR, NAND, NOR, XOR and XNOR using both CMOS and QCA technologies, while the QCA allows more possible design structures for each logic gate to enable optimization of the area. Finally, the proposed QCA-based logic gate design and CMOS-based designs are compared in terms of the design area, cell count and the speed of the designs. QCA designer 2.0.3 and virtuoso CADENCE Computer-Aided Design tools are used for carrying out the work.

Traditional logical equivalence checking (LEC), which plays a major role in the entire chip design process, faces challenges of meeting the requirements demanded by the many emerging technologies that are based on logic models different from the standard complementary metal oxide semiconductor (CMOS). In this article, we propose an LEC framework to be employed in the verification process of superconducting electronics (SCE). Our LEC framework is compatible with the existing CMOS technologies and can also check features and capabilities that are unique to SCE. For instance, the performance of nonresistively biased single-flux quantum (SFQ) circuits benefits from ultradeep pipelining, and verification of such circuits requires new models and algorithms. We, therefore, present the multicycle input dependency circuit model which is a novel model representation of design to explicitly capture the dependency of primary outputs of the circuit on sequences of internal signals and inputs. Embedding the proposed circuit model and several structural checking modules, the process of verification can be independent of the underlying technology and signaling. We benchmark the proposed framework on postsynthesis SFQ and 4-phase adiabatic quantum flux parametron netlists. Results show a comparative verification time of SFQ circuit benchmark, including 16-bit integer divider and ISCAS’85 circuits with respect to the ABC tool for similar CMOS circuits.

The current manuscript aimed to study a differential active balun circuit in terms of the small-signal analysis, implemented in a standard 90-nm complementary metal-oxide semiconductor (CMOS) technology. Small-signal or alternating current (AC) response or frequency response of the active balun determines the maximum frequency of operation and the effective bandwidth of the circuit. With the analysis, the active balun circuit could be modeled and designed to achieve gain or attenuation at the desired frequency of operation. Design tradeoffs are inevitable and are carefully considered in the analysis and design. Eventually, the differential active balun design achieved a gain difference better than 1 dB and a phase difference of 180°±10° or better at the frequency of operation of 5.8 GHz, comparable to previous designs and researches.

Primary cultures of human embryonic kidney (HEK) cells exhibit an in vitro life span of approximately 15 to 20 generations. We report here that transfection of HEK cells with the early gene region of the SV40 DNA tumor virus results in a five-fold increase in cell life span. These cells with extended life span were morphologically similar to normal HEK cells, retained their attachment-dependence for growth and ceased growth at confluence. After 70 to 90 generations in vitro, the transfected cells entered a crisis period, marked by continued basal metabolism in the absence of cell division. Two human kidney cell lines of indefinite life span were isolated from clonal populations of these transfected cells in crisis. These “immortal” HEK cells also demonstrated relatively little evidence of oncogenic transformation, although their morphology and growth characteristics did differ somewhat from the primary HEK cells and the HEK cells with extended life span.

Decimal arithmetic is gaining more attention by researchers due to their importance in many human-centric applications. Hardware implementations of decimal arithmetic are preferable over their software counterparts as the former leads in performance especially when it comes to real-time applications. Decimal addition is a main decimal operation as most of the other decimal operation can be implemented using decimal addition. Complementary Metal Oxide Semiconductor (CMOS) technology has the advantage of reducing the average power consumption and the propagation delay in digital systems. Decimal adders can be designed as a ripple carry addition (RCA) structure or as a carry look-ahead addition (CLA) structure with the latter being faster with extra hardware cost. This work proposes two CMOS-based carry look-ahead decimal adders (CLDAs) that can be used within any decimal arithmetic unit. Operands of 1-digit size, 2-digit size, 3-digit size, and 4-digit size are investigated. The Boolean logic for each of the proposed CLDAs is developed and the CMOS realization is provided. The circuit of each of the proposed CLDAs is simulated with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$45~nm$ </tex-math></inline-formula> technology library using the LT-SPICE spice simulation tool. The simulation shows promising results in terms of speed, power, and power delay product (PDP).

In this article, a three-stage and five-stage voltage-controlled oscillator (VCO) using current starved configuration has been proposed. Among the two, only a three-stage VCO gives the required bandwidth of 5 GHz. Current starved VCO is designed using complementary metal oxide semiconductor (CMOS) technology. The oscillating output frequency bandwidth (2–7 GHz) is considered as the main objective for the proposed circuit. The proposed three-stage VCO circuit uses low supply voltage of 1 V, low power of 29.93 uW. Transient analysis and periodic steady state (PSS) analysis are performed, and after simulation, a wide frequency bandwidth of 5 GHz was obtained. The phase noise for the three-stage VCO at 1 GHz is −132 dBc/Hz. The circuit has been designed in Cadence Virtuso using gpdk 45 nm CMOS technology with supply voltage of 1 V.

We implanted high energy boron to create a heavily doped ground plane in Cz wafers in order to replace p/p/sup +/ episubstrates in deep submicron complementary metal-oxide semiconductor (CMOS) technology. Devices manufactured on Cz wafers with a 1.5 or 1.6 MeV, 1/spl times/10/sup 15/ cm/sup -2/ boron implanted ground plane have superior latch-up immunity as compared to devices on epiwafers. Improvements in latch-up suppression were observed for all isolation spacings. Diode leakage was lower in high dose buried-layer substrates than in episubstrates, while gate oxide integrity was equivalent. For the first time, buried layer substrates have been shown to duplicate or exceed the performance of episilicon simultaneously for all relevant CMOS transistor and circuit parameters.

We have confirmed the basic performance of a new logic intellectual property (IP) compatible (LIC) embedded dynamic random access memory (eDRAM) with cylinder capacitors in the low-k/Cu back end on the line (BEOL) layers. The LIC-eDRAM reduces the contact (CT) height, or essentially the RC delays due to the parasitic component to the contact. By circuit simulation, a 28-nm-node LIC-eDRAM with the reduced CT height controls the logic delay with Δτd < 5% to that of 28-nm-node standard complementary metal oxide semiconductor (CMOS) logics, enabling us ensure the logic IP compatibility. This was confirmed also by a 40-nm-node LIC-eDRAM test-chip fabricated. The 40-nm-node inverter delays in the test-chip were controlled actually within Δτd < 5%, referred to those of a pure-CMOS logic LSI. Meanwhile the retention time of the DRAM macro was in the range of milliseconds, which has no difference to that of a conventional eDRAM with a capacitor-on-bitline (COB) structure. The LIC-eDRAM is one type of BEOL memory on standard CMOS devices, and is sustainable for widening eDRAM applications combined with a variety of leading-edge CMOS logic IPs, especially beyond 28-nm-nodes.

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

A Single-Cell Model of Phase-Driven Control of Ventricular Fibrillation Frequency

The technological essence of silicon photonic integrated circuits is to utilize the mature complementary metal oxide semiconductor (CMOS) technology, or the processes compatible with CMOS technology, to monolithically integrate various kinds of photonic devices in silicon-on-insulator (SOI) substrate. The technology of silicon photonic integrated circuits can fabricate large-scale integrated photonic devices for mass production, providing innovative solutions to the ever-growing demands of high bandwidth, low manufacturing cost, low power consumption in data center, high performance computing center, artificial intelligence and cloud storage. Highspeed optical transceiver modules based on silicon photonic integrated circuits have been commercialized in recent years. Moreover, co-packaged optics (CPO) has become a hot topic and trend for the assembly solution of next generation high-speed switch, and is expected to replace the hot-pluggable optical transceiver modules in the near future.

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. C/sub w/=0.2 pF) delay per stage of 280 ps achieved (W/sub eff//L/sub eff/=15 mu m/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m), a CMOS stage delay of 38 ps for unloaded inverter ring oscillators and 185 ps for loaded NAND are demonstrated. A reduced operating voltage in the range of 2.2-2.5 V is chosen to optimize performance without compromising reliability. Shallow junctions with abrupt profiles are used to minimize device series resistance as well as gate-to-source/drain (S/D) overlap capacitance. Dural poly (n/sup +/ and p/sup +/) gates are used to avoid buried-channel operation pFETs, resulting in superior short-channel characteristics. Poly and S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>