A 1000 frames/s Vision Chip Using Scalable Pixel-Neighborhood-Level Parallel Processing

We developed a new method of pixel-level Analog-to-Digital (A-D) conversion for vision chips, removing Fixed Pattern Noise (FPN) at the same time. Vision chips are CMOS image sensors integrating a processing element (PE) and a photodetector (PD) in each pixel. The chip can handle high frame rate images in real time because its processing speed is high due to the parallel processing and also because it does not need high-bandwidth communication. Pixel-level A-D conversion is an essential technology for vision chips because digital operations must be performed in each pixel. The vision chip, which we have developed, contains a programmable PE in each pixel, and it directly controls the behavior of the PD with the use of the software. In our developed method, the chip controls the reference voltage to cancel the FPN by using this feature. We applied this method to our vision chip, and confirmed that the FPN was reduced and the sensitivity improved. We made a test chip including only PDs to solve the problem on the existing vision chip. As a result of applying this method to the test chip, the detectable minimum illuminance improved about 40 times in comparison with applying our existing method.

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31 μm pitch. Each processor element includes 14 bits of digital memory in addition to seven analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1 μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18 μm CMOS technology.

A new architecture for pixel-level parallel image processing in the pulse domain for CMOS vision chips has been developed. Image processing such as edge enhancement, edge detection, and blurring are realized based on suppression and promotion of digital pulses; the pixel value is represented by the frequency of digital pulses by use of a pulse-frequency modulation (PFM) photosensor or that with an in-pixel 1-bit analog-to-digital converter. The proposed architecture is suitable for low-voltage operation in deep-submicrometer technologies because the image processing is implemented by 1-bit fully digital circuits with a small number of logic gates. The principles of the image processing are addressed. We have fabricated a 16 /spl times/ 16-pixel prototype vision chip. The relationship between illumination and the output pulse frequency is characterized. Step responses of the prototype vision chip for fundamental image processing operations show good agreement with those expected by correlation-based spatial filtering. A simple image binarization method specific to our architecture is also presented. The histograms of the intervals of the output pulses after image processing show multiple peaks, which indicates that averaging of the intervals is required for longer periods to achieve higher image-processing quality. To improve the linearity of pulse frequency dependence on illumination, usage of random clocks is discussed.

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31μm pitch. Each processor element includes 14 bits of digital memory in addition to 7 analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18μm CMOS technology.

BackgroundMeta-analysis suggest that processing speed deficit is the largest single cognitive impairment in schizophrenia. Processing speed predicts functional outcome and indicates a vulnerability marker for schizophrenia. Several authors have proposed that abnormalities in white matter is related to reduced processing speed in schizophrenia. The purpose of this research was to investigate the relationship between processing speed and structural properties of white matter pathways in schizophrenia and healthy controls.MethodsThe data using this study were from the SchizConnect. Participants included 64 patients with schizophrenia and 71 healthy controls. Diffusion tensor imaging(DTI) method was used to measure fractional anisotropy along white matter tracts. Group differences in white matter integrity-inferred from fractional anisotropy (FA), processing speed, verbal memory were examined. Mediation analysis were applied to inspect the relationship between FA and cognitive performance.ResultsParticipants with schizophrenia had significantly reduced processing speed, verbal memory deficits, and whole-brain fractional anisotropy deficit. There were significant group differences in white matter integrity of the left thalamus occipital, right extreme capsule, and right thalamus occipital. FA in left thalamus occipital and right extreme capsule mediated group differences in processing speed, but not other cognitive domains.DiscussionStudy findings indicate that mediation effect of processing speed is regional tract-specific. These finding suggest that the structural integrity of white matter tracts associated with left thalamus occipital, right extreme capsule is closely related to reduced processing speed in schizophrenia, but not verbal memory and verbal learning.

Season-independent cognitive deficits in seasonal affective disorder and their relation to depressive symptoms

Mental speed is a common concept in theories of cognitive aging, but it is difficult to get measures of the speed of a particular psychological process that are not confounded by the speed of other processes. We used Bundesen's (1990) Theory of Visual Attention (TVA) to obtain specific estimates of processing speed in the visual system controlled for the influence of response latency and individual variations of the perception threshold. A total of 33 non-demented old people (69-87 years) were tested for the ability to recognize briefly presented letters. Performance was analyzed by the TVA model. Visual processing speed decreased approximately linearly with age and was on average halved from 70 to 85 years. Less dramatic aging effects were found for the perception threshold and the visual apprehension span. In the visual domain, cognitive aging seems to be most clearly related to reductions in processing speed.

ABSTRACTA reduction in processing speed is widely reported in phenylketonuria (PKU), possibly due to white matter pathology. We investigated possible deficits and their relationships with executive functions in a sample of 37 early-treated adults with PKU (AwPKUs). AwPKUs were not characterized by a generalized speed deficit, but instead their performance could be explained by two more specific impairments: (a) a deficit in the allocation of visuo-spatial attention that reduced speed in visual search tasks, in some reading conditions and visuo-motor coordination tasks; and (b) a more conservative decision mechanism that slowed down returning an answer across domains. These results suggest that the impairments in executive functions seen in AwPKUs are not the consequence of a generalized speed deficit. They also suggest that processing speed is linked to the efficiency of a particular cognitive component and cannot be considered a general function spanning domains. Similarities with patterns in ageing are discussed.

Cognitive impairment in children and adolescents living with perinatal HIV disease in the ART era: a meta-analysis

We have designed and constructed a column parallel vision (CPV) system to realize an intelligent and general purpose image processing system with higher frame rate within 1 millisecond. The system consists of an original designed photo detector array (PDA) with high frame rate, a parallel processing unit with fully parallel processing elements (PEs), and a controller for PDA and PEs. The column parallel architecture enables the PDA 1 millisecond frame rate with 256 analog levels which is required for industrial image processing and measurements. The parallel processing unit has been fabricated by using FPGAs and has 128 X 128 PEs to perform the fully parallel image processing. The PEs have the S<SUP>3</SUP>PE architecture which has SIMD type parallel processing flow, and was constructed only 500 transistors suitable for integration in future. Since the PEs are operated by control signal from the controller, we can achieve desired image processing task to the system by changing the software. We have demonstrated that the system can be worked as a tracking system. The experimental results show the system was realized high speed feedback loop as 1000 frame/s including the tracking operation with noise reduction, matching (self-window algorithm) and moment calculation.

Cognitive decline, related at least in part to reduced processing speed and lower working memory, is a major problem in paediatric and adult patients with sickle cell anaemia (SCA)1,2 and affects quality of life. Multiple studies investigating the association between quantitative and qualitative neuroimaging findings and cognition have had mixed results. Hence, the aetiology of cognitive decline in this population is not clearly understood. Cerebral atrophy on magnetic resonance imaging is noted in the literature but few studies have investigated the association between brain volumes and cognition. White matter microstructural integrity and white matter hyperintensities have been associated with reduced processing speed index (PSI).3 However no study has investigated the association between white matter volumes and PSI in the SCA population. Total subcortical volumes have also been noted to be lower in SCA children and adults. Only one study has investigated the association between total subcortical volumes and working memory index (WMI) in adults.4 Moreover, several studies in the past have noted age related decline in total brain volume as well neurodevelopmental delay in grey matter volume growth.5,6 Most of the developmental trajectory data in the literature comes from longitudinal data sets with limited samples and without control groups. Hence, for the purpose of this study, we investigated the association between regional brain volumes (white matter volumes and total subcortical volumes) and cognition (processing speed index and working memory index) in 129 SCA patients aged 8 – 64 years (66 male) and 50 controls (21 males). Participants were enrolled in two studies - the Sleep Asthma Cohort (SAC) and the Prevention of Morbidity in SCA (POMS) trial. We hypothesized that white matter volumes would predict processing speed index and total subcortical volumes would predict working memory index in SCA patients as well as controls. We also hypothesized that the developmental trajectories for regional brain volumes and cognitive variables would differ between patients and controls. Separate multiple linear regression models for males and females revealed that WMV predicted processing speed index(p=.019) and total subcortical volumes predicted working memory index (p=.025) in male patients only. Age (p=.003) and socioeconomic status (p=.03) also independently predicted PSI in male patients. Individual subcortical regions predicting WMI were statistically significant for left and right thalamus only in male patients. Haemoglobin and age emerged as the best predictors of cognitive decline in patients. Comparison of developmental trajectories between patients and controls revealed that only processing speed was significantly delayed at 8 years. The rate of development for all variables was lower in SCA patients and age-related decline was accelerated in patients as compared to controls. We speculate that early cerebral haemodynamic compromise may contribute to long term cognitive decline in patients. We also highlight that male SCA patients are particularly vulnerable to SCA disease severity. Hence, timely intervention to stabilise haemoglobin levels, especially in males, should be considered. Limitations include lack of stratification by SCI and age (adults and children separately) and the possibility that we were underpowered to detect effects in females.

BackgroundMicrostructural brain lesions have been linked to cognitive health. However, their combined effect and the role of the cognitive reserve (CR) remain unclear. We investigated the interplay of microstructural brain lesions and cognitive reserve in cognitive function in middle‐aged and elderly adults.MethodThis study used data from a prospective cohort of 26,490 UK Biobank participants in the MRI substudy. Markers of microstructural brain lesions included fractional anisotropy (FA), mean diffusivity (MD), intracellular volume fraction (ICVF), orientation dispersion (OD) indices, and isotropic volume fraction (ISOVF), which were estimated using diffusion magnetic resonance imaging (dMRI). Processing speed, reasoning, attention, executive function, and memory were assessed with neuropsychological tests, from which composite scores were derived. The composite CR indicator was generated from early‐life education, midlife occupation, physical activity, and social activity and was dichotomized into low and high CR based on mean CR score. We used multivariable linear regression models to examine the relation between markers of microstructural brain lesions and cognitive function while taking into account the potential interaction (interplay) of brain lesions and CR on cognitive function.ResultControlling for sociodemographic, vascular, and genetic factors, decreased FA and ICVF and increased MD, as markers of impaired integrity of white matter microstructure, were significantly associated with lower composite z‐score of processing speed, attention, and executive function. Reduced ISOVF was associated with higher z‐score of processing speed [multivariable‐adjusted β‐coefficient=‐0.03. 95% CI ( ‐0.041, ‐0.019), p&lt;0.001]. In the stratified analysis by levels of CR, decreased FA and ICVF were significantly associated with lower z‐scores of reasoning and memory, respectively, only in participants with low CR.ConclusionThis study suggests that impaired integrity of white matter microstructure is associated with reduced processing speed, attention, and executive function and that high CR could modify the association of microstructural brain lesions with cognitive function (e.g., memory and reasoning).

Simultanagnosia, an impairment in simultaneous object perception, has been attributed to deficits in visual attention and, specifically, to processing speed. Increasing visual attention deficits manifest over the course of Alzheimer's disease (AD), where the first changes are present already in its symptomatic predementia phase: amnestic mild cognitive impairment (aMCI). In this study, we examined whether patients with aMCI due to AD show simultaneous object perception deficits and whether and how these deficits relate to visual attention. Sixteen AD patients with aMCI and 16 age-, gender-, and education-matched healthy controls were assessed with a simultaneous perception task, with shapes presented in an adjacent, embedded, or overlapping manner, under free viewing without temporal constraints. We used a parametric assessment of visual attention based on the Theory of Visual Attention. Results show that patients make significantly more errors than controls when identifying overlapping shapes, which correlate with reduced processing speed. Our findings suggest simultaneous object perception deficits in very early AD, and a visual processing speed reduction underlying these deficits.

We present the pre to post bilateral globus pallidus interna (GPi) deep brain stimulation neuropsychological profiles of a 69-year-old patient with a 12-year history of X-linked dystonia-Parkinsonism (XDP). Pre-operative cognitive function was impaired in almost all domains and this impaired performance was not dependent on his medications. Following DBS, changes in neuropsychological functioning were examined using Reliable Change Indices and standardized z-score comparisons. Results showed reductions in processing speed in the context of stable performance in language and visuospatial domains. Post-operative improvements occurred on a cognitive screening measure, verbal memory, and a test of problem-solving skills. This is the first report on an individual with XDP who was cognitively impaired, but had good outcome following GPi bilateral stimulation to treat debilitating motor symptoms. The possible mechanisms for his stable cognitive performance include the target of his DBS, reduced medication dosage, and improvement in dystonia that may in turn have reduced patient's pain.

The availability of low-cost, readily programmable digital hardware offers numerous opportunities for novel modeling and control approaches. One such opportunity is the realization of hardware modeling of distributed dynamic systems. Such models could be useful for control algorithms that require high-fidelity models operating in real-time. The ultimate goal is to utilize digital systems with programmable hardware. As a proof-of-concept, multiple discrete microcontrollers have been used to emulate how programmable hardware devices may be used to simulate a distributed vibrating system. Specifically, each microcontroller is treated as a single vibrating mass with stiffness and damping coupling between the masses. Each microcontroller has associated position and velocity variables. The only additional knowledge required to compute the acceleration of each “mass” is thus the position and velocity of each immediate neighboring mass/microcontroller. The computation time is independent of the number of nodes; adding nodes results in no reduction in processing speed. Consequently, the computational approach will be applicable to very high order models. Practical implementation of such models will require digitally programmable hardware such as field-programmable gate arrays (FPGA), however an added benefit will be a still greater reduction in cost, as multiple microcontrollers are replaced by a single FPGA. It is expected that the hardware modeling approach described in this work will have application not only in the field of vibration modeling and control, but also in other fields where control of distributed dynamic systems is desired.