Pulse-Domain Digital Image Processing for Vision Chips Employing Low-Voltage Operation in Deep-Submicrometer Technologies

A vision chip based on pulse frequency modulation (PFM) is proposed as a retinal prosthesis device for use in subretinal implantation. A pixel circuit of PFM has been fabricated using standard CMOS technology. A dynamic range of 40 dB is demonstrated at a low power supply voltage of 1 V. It is found that the competition between the charge current to the photodiode and the photocurrent affects the output pulse characteristics under the conditionds of low power supply voltage and strong light illumination. For in vitro and in vivo experiments, two methods of improving the PFM circuits are considered. One is controlling the pulse frequency. By adding one transistor to the PFM circuit, the output pulse frequency can be experimentally controlled by a factor of two. The other is using a biphasic output, which is required to keep a charge balance in a living body. By introducing differential circuits, the biphasic output has been confirmed by simulation.

In this paper, we propose and demonstrate a new pixel structure of a vision chip for visual recovery of the blind by means of electric stimulation against the retina. We introduce output frequency range control to a conventional pulse frequency modulation (PFM) photosensor. To configure the lower and upper limits of the output pulse frequency suitable for electric stimulation, we added nMOS and pMOS leak transistors and a switched-capacitor filter to an original PFM pixel circuit. We fabricated a test circuit of the improved PFM pixel using a standard 0.6 μm CMOS process. The pulse frequency range was successfully fixed, for example, from 100 Hz to 1 kHz.

Image Processing architecture and algorithms are used for the purpose of improving the image quality and to extract complete information in more precise manner. The need to process in real time has led to implement them on the target device with real time constraints like power and area. To implement image processing algorithms and architecture with the help of high level languages needs more blocks of code apart from inefficient in terms of time constraint. The easiest way to deal with facilitating usage of Xilinx System Generator/XSG blocks, XSG is a tool where we can build our design using pre existing block level components which are captured by using Xilinx block set from library environment and implement as per user requirement. The main responsibility of system generator is Xilinx block sets that provides the package integration with MATLAB Simulink and helps in co- simulating FPGA hardware module. As per part application category, edge detection is a major essential application in medical field for proper diagnosis and correct treatments. Field-Programmable Gate Arrays (FPGAs) have become more popular computing platforms as target device for digital signal processing. The Zynq System on Chip (SOC) is a dual-processor platform with shared memory. This paper describes a fast architecture implementation of Sobel edge detection using the Zynq as a reconfigurable device. Our implementation is to merge both software and hardware using the Vivado and Zynq (SoC). As a result, our implementation is fast in terms of performance compare to the pre existing models. We make a comparison with other conventional edge detection techniques and show that the speed of operation of this design is much faster. This approach is tested over hardware or different gradient test vectors. Finally the algorithms are evaluated for the major essential images from the medical field to extract lasting effect in detecting the edges using gradient factor. The area and power factors are evaluated for reconfigurable hardware i.e, Zynq FPGA.

This paper presents a novel vision chip architecture based on pixel-neighborhood-level parallel processing. In the architecture, an 8-b RISC processing core is embedded in an 8×8 array of digital pixel sensors on the same focal plane. These neighborhood processors (NPs) are tiled in a 2-D array to form the final imager resolution. Program execution is carried out in parallel across the array of pixel-neighborhood processing cores, allowing for direct scalability in terms of resolution, without reduction in processing speed or frame rate. To accomplish this, a compact, low-complexity NP architecture along with a general purpose, 8-b instruction set has been designed and implemented. A prototype vision chip containing an 8×10 array of NPs with a 64×80 resolution has been designed and fabricated in a 0.13-μm 1P8M CMOS fabrication process. The system is reprogrammable and can perform a wide range of image and video processing tasks. Several example algorithms are implemented and tested on the single-chip vision system to demonstrate the functionality of pixel-neighborhood-level parallelism, including 1000-frames/s object tracking.

In this chapter, we become familiar with image analysis and processing. We learn definition and computation of two of the most popular 2D orthogonal image transformations, the 2D discrete Fourier transform (DFT) and 2D discrete cosine transform (DCT). We see how to use them for image filtering in frequency domain. Next, we find out the definition of 2D convolution of matrices and their usage for image filtering, i.e. calculation of local weighted mean values of image pixels. We learn 2D filter weights, the most frequently used for image smoothing (de-noising) and edge detection (masks of Sobel, Prewitt, Roberts, Laplacian). We become also familiar of some non-linear image processing with median and morphological filters (erosion, dilatation). In this chapter, principles of 2D wavelet transform of an image using pair of wavelet low- and high-pass filter are presented in an image processing example/exercise in an image processing example/exercise. Basics of JPEG standard (compression of still pictures) and MPEG standard (compression of moving pictures, i.e., movies) are summarized. Finally, example of image watermarking is shown.

With a remarkable advance in CMOS (complimentary metal-oxide-semiconductor) process technology, a variety of vision sensors with signal processing circuits for complicated functions are actively being developed. Especially, as the principles of signal processing in human retina have been revealed, a series of vision chips imitating human retina have been reported. Human retina is able to detect the edge and motion of an object effectively. The edge detection among the several functions of the retina is accomplished by the cells called photoreceptor, horizontal cell and bipolar cell. We designed a CMOS vision chip by modeling cells of the retina as hardwares involved in edge and motion detection. The designed vision chip was fabricated using CMOS process and the characteristics were measured. Having reliable output characteristics, this chip can be used at the input stage for many applications, like targe tracking system, fingerprint recognition system, human-friendly robot system and etc.

This research explores the design and implementa- tion of an image and video processing platform using recon- figurable FPGA technology. With the increasing demand for real- time, high-performance multimedia processing in modern applications, a flexible and efficient solution is essential. The project utilizes an FPGA-based platform to handle image and video data processing through edge detection, image scaling, and real-time motion detection techniques. By integrating custom- built hardware components, this study aims to provide a low- power, high-throughput solution that meets the requirements of both image and video processing tasks. Materials and methods involved using Xilinx Virtex-II Pro FPGA for hardware imple- mentation, alongside embedded memory processors and multi- functional design elements such as zoom-in/out utilities. The system was evaluated through several experimental procedures, using various image and video datasets, to measure performance in terms of speed, resource utilization, and power consumption. Results indicated that the system achieved notable improvements in terms of efficiency, utilizing 25% of logic resources, 55% of on- chip memory, and 180mW of power. The discussion focuses on the adaptability of FPGA-based systems in meeting the diverse needs of multimedia processing, emphasizing scalability and low power consumption. In conclusion, the reconfigurable FPGA platform provides a versatile and efficient environment for image and video processing. The system’s resource efficiency, scalability, and potential for further enhancements make it a promising candidate for future multimedia applications. Keywords-Reconfigurable FPGA Architecture, Video and Image Processing, Edge Detection, Image Rescaling.

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31 μm pitch. Each processor element includes 14 bits of digital memory in addition to seven analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1 μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18 μm CMOS technology.

With increasing applications of image processing in manufacturing, it has become necessary to provide industry with powerful as well as flexible means of adapting the technology to the solution of different kinds of tasks at hand. Besides the standard components of an image processing system, the availability ofvarious software tools to fill the gap between design, digitization, measurement and the manufacturing phases should be emphasized. The users could e.g., desire to transfer grabbed images into certain computer graphics data format for further processing. They may want to apply image processing for the measurement of machine parts interactively or automatically, or they may want to convert the pictures processd, e.g. with edge detectors, into some CAD data format, or even to generate a numerical control file to machine the parts directly from the image processing data. With this motivation, two software packages FIPS—Flexible Image Processing System, and IQIS— Integrated QUality Inspection System have been developed for manufacturing and quality inspection and have been used by industry for various purposes from simple image digitization and processing, luminance adjustment, data and file format conversion, generation of control files for numerical control in laser cuffing, to direct control of robot movement, and interactive as well as automatic machine part measurement.

The ULowell Data Flow Project combines dataflow hardware, dataflow software, and a data flow development environment. The hardware component, a data flow coprocessor card, utilizes seven NEC 7281 Image Pipelined Processors. Each chip models a static dataflow computation and is programmable. The coprocessor was designed and implemented by ULowell personnel and uses an AMIGA 2000 as a host. The software component currently consists of a library of data flow image processing algorithms and an evolving software development environment. Currently the image processing library includes typical imaging operations such as: edge enhancement, filtering, histogramming, and affine transformation. The software development environment (SDE) is depicted in Figure 1. The SDE contains a Data Flow Graph Editor which programmers use to design their data flow code. The data flow algorithm can then be converted directly into NEC data flow assembly code which is then assembled using the ULowell Data Flow Assembler. The assembler differs from NEC's assembler in that it can produce relocatable code. The object code output of the assembler is given to the Data Flow Resource Manager. The resource manager monitors the available resources within the chips. Thus, if a single process does not totally utilize a chip's table space or memory, then a second process may be concurrently loaded onto the same chip. The ability to have multiple data flow processes coexisting within a single chip is unique to the ULowell environment. The data flow resource manager can download and monitor code to either the hardware or to a software simulator/debugger. The simulator/debugger can monitor and trace data flow tokens as they proceed through the chip. Output of the simulator/debugger can be fed back into the data flow graph editior to visually trace token flow through the original program design. The last component of our SDE is a High Level Language translator which can compile programs written in SISAL, a high level language for parallel computation, down to NEC 7281 assembly language. We have already implemented the relocatable assembler, and the data flow resource manager. Prototype versions of the high level translator, simulator/debugger and graph/editor are currently being implemented.

In addition to causing damage to vehicles, road defects are one of the main causes of vehicle accidents which lead to loss of human lives. Many methods of detecting defects have been introduced over the years to reduce the consequences of these defects. One of these methods is image processing. Use of image and video processing has many applications in medicine, science, agriculture, and defect detection in structures. It has been used for defect detection on roads because timely detection and analysis of defect is very important for road serviceability and safety of the people. Detection of a defect by image processing broadly follows some of the basic steps which include feature extraction, edge detection, morphological operators, and training of data. Different approaches are used for various kinds of defect detection and analysis which have replaced the manual inspection method of roads saving time and resources. This chapter discusses the basic steps involved in defect detection using image processing along with existing systems that use machine learning and artificial intelligence for the detection of defects from a distance. To write this chapter, papers on the topic of image and computer vision-based defect detection systems have been consulted.

Several problems are encountered in modeling and processing of many life science applications such like tissue engineering, bioacoustics, and food processing detection. Recently, various image processing techniques have been developed in an attempt to solve these problems. Due to the rapid advance and high number of researches included in such field, there is always a room for improvement. In this work, advanced image processing approaches are presented and applied to different life science applications. The first approach utilizes image processing in the generation of micro-scaffolds for tissue engineering modeling. Furthermore, a spectrogram enhancement approach is developed to improve the pattern detection of weevils existence in grain storage, based on their detected and identified sounds. Finally, a novel edge detection method applied on intramuscular fat recognition is presented based on the energy and skewness as two smoothed versions of the meat image. Results, in comparison to experimental data, offer a maximum error of 7.81% in the specified detection process. 1. Material and Method 1.1 Generation of micro-porous approach The difficulty of modeling such complex micro-structures always lies in retrieving the geometry into the solver as edges. Edge detection algorithms are based upon highlighting discontinuities in images and were first developed for satellite images. The technique has become well-known and was further developed and widely used for other image processing applications. During the conventional detection procedures, usually all the image size is processed, which leads to redundant calculations of areas containing no edge information. In this study a redundant avoiding algorithm is developed which searches for the threshold value in the image and then propagates around it in a 2-D lattice in eight directions figure 1.1, until an edge is hit. Figure 1.1 The scanning procedure for gradient changes propagates in an eight directional lattice until an edge is hit 1.2 Spectrogram enhancement in bioacoustics This approach is based on detection of the sound pattern edges in the crest factor image, as shown in figure 1.2 and 1.3, which behaves as a smoothed version of the spectrogram image and avoids the use of edge detectors prior smoothing filters and their scaling constraints. Figure 1.2 Spectrogram with 40 dB limited dynamic range Figure 1.3 Crest factor distributions (left), the scaled crest factor image of the spectrogram (right). 1.3 Edge detection for intramuscular fat recognition A novel edge detection method applied on intramuscular fat is presented based on the energy and skewness as two smoothed versions of the meat image, as shown in the flow chart given in figure 1.4. Figure 1.4 flow chart edge detection 2. Results 2.1.Generation of micro-porous Approach The conventional approach for edge detection is based upon either thresholding the first derivative (gradient) of the image or locating zero crossings of its second derivative (Laplacian).The sample used, figure 2.1, for this simulation was of size 3 mm, 350 μm and 350 μm in z-direction, x-direction and y-direction, respectively. The geometry was uploaded on the solver by collective segmenting and edge detection techniques. The method has proven time saving and as well enables the possibility of parallel processing of the image, as each threshold value can be scanned and dealt with independently. After the predictions of the edges, the 2-d binary edge images are assembled forming a 3-D binary file of the scaffolds figure 2.1. Figure 2.1 From the micro-CT images 430 hundred 2-D binary edge images are assembled forming a 3-D binary file of the scaffolds 2.2.Spectrogram enhancement in bioacoustics The spectrogram enhancement approach is compared to other enhancement approaches, including multiband spectral subtraction and wavelet packet decomposition, for different structure bioacoustics calls including bats (ultrasound range) and birds (acoustic range), with additive white Gaussian noise added across a range of signal to noise ratios. Results measured subjectively and objectively, indicate that the proposed method is promising for efficiently spectrogram enhancing while preserving its temporal and spectral accuracy, as shown in figure 2.2. Figure 2.2 (a) One of Sitta Canadensis bird calls at SNR = 20 dB, and its enhanced spectrogram by (b) BP, (c) MBSS, (d) WF, (e) WPD, and (f) the proposed method approaches. 2.3.Edge detection for intramuscular fat recognition The generation of micro-scaffolds approach is applied on a sample meat image, which is scanned line by line and every noticeable variance in the color values or the grey levels is captured and the local thresholds values are estimated according to the highest drop gradient value. The local threshold values are averaged to estimate the global threshold for the whole image, as shown in figure 2.1. Figure 2.3 an image for a meat with fat (a), the x y scan of the image which does not show all the fat details (b) and the lattice scan of the image showing more details of the fat, as circled by red (c). For intramuscular fat, the developed edge detection approach is used to predict the fat content in marbled meat images, as shown in figure 2.3. Figure 2.4 (a) original marbled meat images, (b) edges images using the proposed method (c) detected fat regions, and (d) the percentage of fat content Conclusion As observed in the different approaches there is always a room for improvement that minimize the error observed in the specified detection process. The methods have proven time saving and as well enables the possibility of parallel processing of the image that leads to a more efficient performance highly desirable for industrial applications.

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31μm pitch. Each processor element includes 14 bits of digital memory in addition to 7 analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18μm CMOS technology.

Hardware support for image processing is very important in emerging applications such as desktop publishing, medical imaging, and multimedia. In the past, computational needs for intensive image processing tasks, such as image analysis of satellite data and pattern recognition, were satisfied with custom, complex, and expensive image processing architectures [1], [2] However, the latest scientific workstations have enough compute power for low-cost desktop image processing. Furthermore, traditional image processing operations, such as texture mapping and warping, are now combined with conventional graphics techniques. Hence, there is an increased interest for accelerated image and video processing on low cost computational platforms, such as personal computers and scientific workstations.

An analytical expression for the myoelectric signal was derived using the integral pulse frequency and amplitude modulation (IPFAM) approach. The results indicate that, in the frequency domain, the general envelope of the EMG spectrum is affected primarily by the motor unit action potential (MUAP) and its interaction with the pulse amplitude modulation (PAM) and pulse frequency modulation (PFM) processes. Furthermore, the component associated with force modulation co-exists at its modulating frequency with factors related to the MUAP. Therefore, the conventional low-pass filtering is not adequate for reconstructing dynamic muscular force signals from nonstationary myoelectric signals obtained during locomotion.