A 12-B 10-MSAMPLES/S CMOS SWITCHED-CURRENT DELTA-SIGMA MODULATOR

This paper presents a study of the effects of the op-amps' finite DC-gain (FDCG) and nonlinear DC-gain (NLDCG) on switched-capacitor (SC) delta-sigma (/spl Delta//spl Sigma/) modulators. Starting with the theoretical point of view, these two nonidealities are analytically studied, modeled and their effects on the overall signal to noise plus distortion ratio (SNDR) of a modulator are discussed. Several simulations are performed to clarify the various effects of FDCG and NLDCG on a typical single loop modulator. It is shown that although FDCG of the first stage of the modulators has always attracted the most concerns on /spl Delta//spl Sigma/ literature, NLDCG of the first stage could have a worse effect in the output SNDR due to its nonlinear nature which directly manifests itself as a distortion error and increases the in-band noise of the modulator.

A new architecture for a CMOS A/D converter overcomes many of the known problems in the parallel operation of multiple pipelined stages. The input signal is sampled in one channel, and after quantization to 4 b, the residue is distributed into many channels. A prototype implemented in 1-/spl mu/m CMOS achieves 60 dB signal-to-noise plus distortion ratio (SNDR) at low conversion rates, with a resolution bandwidth of greater than 20 MHz. The SNDR drops by 3 dB at a 95 MHz conversion rate, and the bandwidth remains the same.

This paper presents a low-voltage low-power pipelined ADC with 1V supply voltage in a 90nm CMOS process. A new architecture is proposed to reduce the power consumption in high-speed pipelined analog-to-digital converters (ADCs). The presented architecture utilizes a combination of two current power-reduction techniques, double sampling and amplifier sharing. To decrease the power dissipation more efficiently, the stage scaling technique has been applied to the ADC and dynamic comparators have been used in sub-ADCs. Using this approach, a 10-bit 200MSample/s pipelined ADC has been designed in a 90nm CMOS technology. HSPICE simulation results show a signal-to-noise plus distortion ratio (SNDR) of 58.5dB with a 9.375MHz, 1-V P-P,diff input signal while consuming only 30.9mW power from a 1V supply voltage.

A 7-bit 400 MS/s sub-ranging flash analog-to-digital data converter (ADC) with short latency is presented. To improve the sampling rate, the fine pre-amplifiers combined with the switched current sources are adopted instead of the switch matrix in a conventional sub-ranging ADC. The proposed architecture avoids the noise coupling from the switches and reduces the parasitic capacitances, which limit the resolution and bandwidth of a sub-ranging ADC. This prototype has been fabricated in 0.18um CMOS process. It dissipates 108 mW with a supply of 1.8 V and occupies the active area 0.64mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured performance achieves the signal to noise plus distortion ratio (SNDR) of 40 dB at sampling rate of 400 MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.9-LSB and ±0.7-LSB, respectively.

We study amplify-and-forward (AF) relay networks operating with source and relay amplifier distortion, where the distortion dominates the noise power. The diversity order is shown to be 0 for fixed-gain (FG) and 1 for variable-gain (VG) if distortion occurs at the relay; if distortion occurs only at the source, the diversity order will be 1 for both. With e β = N 0 /η β (N 0 the noise power, η β the distortion power at node β ∊ {S, R}, the source or relay), we demonstrate the emergence of what we call an e-critical signal-to-noise plus distortion ratio (SNDR) threshold (a threshold that emerges when min{e β } becomes small) for both forwarding protocols. We show that crossing this threshold in distortion limited regions will cause a phase transition (a dramatic drop) in the network's outage probability. Thus, small reductions in the required end-to-end transmission rate can have significant reductions in the network's outage probability.

A quadrature bandpass /spl Delta//spl Sigma/ modulator IC facilitates monolithic digital-radio-receiver design by allowing straightforward "complex A/D conversion" of an image reject mixer's I and Q, outputs. Quadrature bandpass /spl Delta//spl Sigma/ modulators provide superior performance over pairs of real bandpass /spl Delta//spl Sigma/ modulators in the conversion of complex input signals, using complex filtering embedded in /spl Delta//spl Sigma/ loops to efficiently realize asymmetric noise-shaped spectra. The fourth-order prototype IC, clocked at 10 MHz, converts narrowband 3.75-MHz I and Q inputs and attains a dynamic range of 67 dB in 200-kHz (GSM) bandwidth, increasing to 71 and 77 dB in 100- and 30-kHz bandwidths, respectively. Maximum signal-to-noise plus distortion ratio (SNDR) in 200-kHz bandwidth is 62 dB. Power consumption is 130 mW at 5 V. Die size in a 0.8-/spl mu/m CMOS process is 2.4/spl times/1.8 mm/sup 2/.

Clock feedthrough (CFT) error is one of the most important problems for switched current (SI) circuits. This paper proposes a SI circuit which can reduce CFT error drastically. The proposed circuit will theoretically reduce both signal-dependent and independent errors by using CMOS switches under a fixed and appropriate bias. Although conventional circuits based on a similar idea need operational amplifiers or additional capacitors, the circuit proposed in this paper requires only MOSFETs. The proposed circuit can reduce clock feedthrough current with less power consumption and chip area compared to those of conventional circuits. An automatic tuning circuit, which controls the gate potential appropriately, is also proposed. Simulation results demonstrate the effectiveness of the proposed circuits.

SummaryThe performance of a switched‐capacitor circuit strongly depends on its analog switches. This paper introduces a new technique to design a high‐precision analog metal‐oxide‐semiconductor switch for switched‐capacitor applications. The accuracy of analog switches is a critical parameter to determine overall performance of the discrete‐time analog systems. To satisfy the accuracy requirements of the switch, a novel technique to minimize the charge injection and clock feedthrough errors by using a very simple structure is proposed. Moreover, an innovative approach to increase the OFF resistance of the switch and consequently minimizing its leakage current is presented. To evaluate the performance of the proposed switch, simulations are done in TSMC 0.18μm standard complementary metal‐oxide‐semiconductor technology with BSIM3V3 device models. The ON and OFF resistances of the switch are one of the most important factors that should be considered while investigating analog switches. The ON resistance of the proposed switch is less than 560Ω over entire input signal range which completely satisfies the tracking bandwidth requirements. In addition, since the proposed switch provides an ultrahigh OFF resistance in the range of several GΩs, the leakage current of the proposed switch is negligible. Simulation results also show that switch‐induced errors are significantly eliminated by using the proposed cancellation technique. The output error charge due to charge injection and clock feedthrough over a wide range of input signal variation is very low (less than 1.6 fC). Moreover, simulation results show that the proposed switch achieves signal to noise plus distortion ratio of 80.55 dB, effective number of bits of 13.08, total harmonic distortion of −81.41 dB, and spurious‐free dynamic range of 87.7 dB for a 2.5‐MHz sinusoidal input of 800‐mV peak‐to‐peak amplitude at 200‐MHz sampling rate with a 1.8‐V supply voltage. Consequently, the simulation results verify that the proposed switch can significantly improve the dynamic and static performances of a switched‐capacitor circuit.

A 10-bit 40-MS/s time-domain two-step analog-to-digital converter (ADC) in a 0.18- $\mu \mbox{m}$ CMOS process is presented. The proposed ADC is realized without any high-gain amplifiers and its calibration time requires only 622 clock cycles, which is over 10 times less than prior digitally calibrated ADCs. The measured spurious-free dynamic range (SFDR) and signal-to-noise-plus distortion ratio (SNDR) are 61.3 dB and 53.8 dB at 40 MS/s, respectively. The power and area are 6.1 mW and 0.75 mm2, respectively.

Optical frequency stabilisation and linewidth reduction by the current feedback technique were studied with a multi-electrode DFB laser. In the current feedback technique, phase rotation in the feedback loop, particularly induced by a laser, is the fundamental problem. This problem was resolved by using multielectrode DFB lasers without phase inversion. We simultaneously succeeded in optical frequency stabilisation and linewidth reduction with only one feedback electrical circuit. Optical frequency drift and spectral line-width were reduced to 1/14 and 1/126, respectively, of those in the free-running state. The minimum spectral linewidth obtained was 95 kHz.

An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2/spl times/2-memory array was prototyped according to a standard 0.8 /spl mu/m n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 /spl mu/A /spl les/ I/sub SAMPLE/ /spl les/ 0.75 /spl mu/A. Standby consumption is 6.75 /spl mu/W per cell at I/sub SAMPLE/=0.75 /spl mu/A. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x/sub max/=320 mV/sub pp/ and 2y/sub max/=448 mV/sub pp/, yielding a maximum output swing of 0.9 /spl mu/A/sub pp/. 4QM worst-case nonlinearity is 7.9%.

This paper presents a class-D power amplifier for medium quality sound systems using a second-order passive sigma-delta modulator (ΣΔM). The ΣΔM controls an output power stage consisting of a H-bridge. The loop filter of the ΣΔM was designed using a optimization procedure based on genetic algorithm (GA), that takes into account several parameters. This system was implemented using discrete components and the experimental results show that a DR of 75 dB is achieved with a peak signal-to-noise-plus-distortion ratio (SNDR) of 54 dB.

Multithreshold-voltage CMOS (MTCMOS) has a great advantage of lowering physical threshold voltages without increasing the power dissipation due to large subthreshold leakage currents. This paper presents the embedded SRAM techniques for high-speed low-power MTCMOS/SIMOX application-specified integrated circuits (ASICs) that are operated with a single battery cell of around 1 V. In order to increase SRAM operating frequency, a pseudo-two stage pipeline architecture is proposed. The address decoder using a pass-transistor-type NAND gate and a segmented power switch presents a short clocked wordline selection time. The large bitline delay in read operations is greatly shortened with a new memory cell using extra low-V/sub th/ nMOSs. The small readout signal from memory cells is detected with a high-speed MTCMOS sense amplifier, in which a pMOS bitline selector is merged. The wasted power dissipation in writing data is reduced to zero with a self-timed writing action. A 8 K-words/spl times/16-bits SRAM test chip, fabricated with a 0.35-/spl mu/m MTCMOS/SIMOX process (shortened effective channel length of 0.17 /spl mu/m is available), has demonstrated a 100-MHz operation under the worst power-supply condition of 1 V. At a typical 1.2 V, the power dissipation during the standby time is 0.2-/spl mu/W and that of a 100-MHz operation with a checkerboard test pattern is 14 mW for single fan-in loads.

In this paper, we present a single-bit clock-less asynchronous delta–sigma modulator (ADSM) operating at just 0.25 V power supply. Several circuit approaches were employed to enable such low-voltage operation and maintain high performance. One approach involved utilizing bulk-driven transistors in subthreshold region with transconductance-enhancement topology. Another approach was to employ distributed transistor layout structure to mitigate the effect of low output impedance due to halo drain implants employed in today’s digital CMOS process. The ADSM achieved a characteristic center frequency of 630 Hz. It had an effective signal-to-noise-plus-distortion ratio (SNDR) of 58 dB or effective number of bits (ENOB) 9 b and just 28-nW power dissipation. A detailed analytical model capturing the effect of nonidealities of the individual circuit components is also presented for the first time with a close agreement with experimental results.

A 1.2 V, 10 b, 40 MS/s pipelined ADC fabricated in 0.13µm one-poly eight-metal (1P8M) standard CMOS process with MIM capacitors is presented. This ADC used a novel low-variation on-resistance CMOS sampling switch to improve the nonlinear effect and a two-stage recycling folded-cascode (RFC) amplifier with hybrid frequency compensation for power saving and low voltage supply requirements. By implementing with 2.5-bit/stage and an improved amplifier sharing scheme, very competitive power consumption and small die area can be achieved. A test chip was fabricated for confirmation, a peak signal-to-noise-plus-distortion ratio (SNDR) of 56.76 dB with 40MS/s at 19.3 MHz input signal and a power dissipation of 23.2 mW was achieved.