A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure

This paper presents a fully-dynamic, low-power, and wide-band time-interleaved (TI) noise-shaping (NS) SAR ADC based on the cascade of integrators with feed-forward (CIFF) architecture. Its loop filter and interleaving operation are realized by fully-passive switched capacitor (SC) circuits. Its feedforward summation is implemented by using a multi-path comparator. Moreover, its overall noise transfer function (NTF) is set by device ratios and highly robust against process, voltage, and temperature (PVT) variations. It allows the loop filter poles to be placed close to the unit circle. Comparing to a recently published TI NS SAR ADC based on the error-feedback (EF) structure, this work obviates the need for amplifiers with static current, saving power. It also eliminates the dependence of NTF on the amplifier gain, which is PVT sensitive. A prototype ADC in 40nm process achieves 69.1dB SNDR over 50MHz BW while consuming only 8.5mW from a 1.1V supply, leading to a Walden FoM of 36.3fJ/conv.-step.

This paper presents a novel noise shaping SAR architecture that is simple, robust and low power. It is fully passive and only needs minor modification to a conventional SAR ADC. Through a passive integrator, quantization noise, comparator noise and DAC noise are shaped with a noise transfer function of (1 - 0.75z <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ). Unlike conventional multi-bit delta-sigma ADCs, both the noise transfer function and the error transfer function of DAC mismatches are immune to process-voltage-temperature variations. A prototype chip is fabricated in a 0.13μm CMOS process. At 1.2V and 2MS/s, the chip consumes 61μW power. SNDR increases by 6dB and the Schreier FoM increases by 3dB with OSR doubled. At an OSR of 8, SNDR is 74dB and the Schreier FoM is 167dB.

A 12.1bit-ENOB noise shaping SAR ADC for biosensor applications

This paper presents a band-pass noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) with a second-order modulator which is comprised of a fully passive switched-capacitor (SC) filter and a gain-boosted dynamic amplifier. It employs the error-feedback (EF) structure in a simple method to implement the complicated noise transfer function (NTF) zeros, which enhances the noise-shaping capability by minimally modifying a standard SAR ADC. Designed in 28 nm CMOS process, the prototype of proposed NS-SAR ADC achieves 76.84 dB signal-to-noise and distortion ratio (SNDR) with the bandwidth between 20 and 40 MHz and the FoMw is only 2.24 fJ/step at the oversampling ratio (OSR) of 5.

This paper presents a continuous-time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-band interferers compared to previous designs. In 160 nm CMOS, the prototype chip occupies 0.36 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , achieves 107.2 dB SNR, 106.6 dB SNDR, and 107.3 dB dynamic range in a 24 kHz bandwidth while consuming 590 µW from a 1.8 V supply. This translates into a Schreier figure-of-merit (FoMs) of 183.4 dB and a FoM <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SNDR</inf> of 182.7 dB.

This article presents a third-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which exploits a hybrid error control topology to increase the order of the noise-transfer function (NTF). This scheme is a hybrid of two NS stages, namely, a cascaded integrator feed-forward (CIFF) and an error feedback (EF). This EF-CIFF structure contributes a more effective NS capability and enhances the robustness of the high-order NTF. An improved dither-based digital calibration is developed to mitigate the harmonic distortion caused by the capacitor mismatch. Due to the usage of an averaging filter, this calibration greatly reduces the interference of quantization noise on mismatch extraction while only needing a minimum modification in a standard SAR Topology. Hence, our scheme is simple and inherently robust to the process, voltage, and temperature variation. Based on an 8-bit SAR, our prototype is fabricated in a 130-nm CMOS process. It consumes a 96- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power when operating at a 2-MS/s sampling frequency with a 1.2-V supply. The proposed NS-SAR yields a peak Schreier figure of merit of 170.7 dB with a signal-to-noise-and-distortion ratio (SNDR) of 79.57 dB at an oversampling ratio of 8.

A novel active noise-shaping SAR ADC with on-chip digital DAC calibration is presented. To relax the design of the single op-amp used as an integrator, correlated double sampling (CDS) and correlated level shifting (CLS) were implemented. CDS minimizes the offset of the integrator and reduces the flicker noise, while CLS boosts the gain of the op-amp and reduces the power consumption. Also, a two-step incremental ADC based digital DAC calibration scheme was implemented to cancel the DAC mismatch errors and parasitics effects. The ADC was fabricated in 0.13um CMOS technology. It achieved 85.1dB DR, 82.6dB SNDR and 90.9dB SFDR within a 2kHz signal bandwidth with 32 oversampling ratio (OSR). It consumes 40.8 uW power using a 1.6V power supply.

Flexible and wearable devices are emerging with the developing of the sensors and IoT (internet of the things). The power consumption and volume of such devices are dominant limitations for wearable feature in various applications. To meet the requirements, a photoacoustic receiver system-on-chip (SoC) is developed and fabricated with a novel correlation detection technique based on the early-and-late tracking. Through this method, output SNR of the receiver can be significantly improved. For this, a low power and high sensitivity analog front-end (AFE) with a noise shaping (NS) SAR ADC is implemented. As oversampling is necessary for the accurate delay of digital processing, noise shaping technique is implemented in the SAR ADC. Simulation results show that, the AFE achieves 70 dB dynamic range and 20 μV sensitivity for about 30 dB output SNR. The SAR ADC can obtain 71 dB SNDR under 50MSps sampling rate with the aid of the NS technique. Based on the analog circuits design, the digital part for the detecting technique is also implemented on chip. The whole power consumption is about 15 mW on the TSMC 65 nm CMOS process.

Sigma-delta modulators use a noise-shaping technique to curtail the noise power in the band of interest during digital-to-analog conversion. Error feedback modulator employs an efficient noise transfer function for time varying inputs than any other sigma-delta modulators. However, the efficiency of the conventional noise transfer function degrades and the quantizer saturation issue provokes when the input signal reaches to full scale. This work proposes a new noise transfer function which is a combination of transfer functions of two-stage Feed-forward delays and a novel Hybrid multi-stage noise shaping-error feedback sigma-delta modulator. The noise transfer function of two-stage Feed-forward delays mitigates the concern of quantizer saturation. The noise transfer function offered by the Hybrid multi-stage noise shaping-error feedback architecture provides sustainable solutions to limit cycles and idle tones. The simulation concludes that the proposed noise-shaping approach obtains comparatively high signal-to-quantization noise ratio than the conventional error feedback modulators. Other performance parameters like spurious-free dynamic range, effective number of bits and signal-to-noise plus distortion ratio are also significantly improved.

The performance of a sigma-delta analog-to-digital converter (ADC) critically depends on one or more of the main three parameters: over-sampling ratio, the order of the modulators, and the number of bits used. Increasing each one of these parameters presents a degree of challenge (i.e., the increase in the over-sampling ratio is limited by the technology and the power consumption requirement). This paper presents a method to obtain high order noise shaping with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -path architectures that are based on first-order or second-order modulators. The desired noise transfer function (NTF) is obtained by suitable cross-coupling paths. The method was applied to a two-path first-order modulator for obtaining a second-order noise shaping. The performances of the proposed sigma-delta ADC were verified at the behavioral and transistor level implemented in 90-nm CMOS technology.

This paper presents a novel architecture for a multistage (MASH) voltage controlled oscillator based analog-to-digital converter (VCO-ADC). The innovation allows control over the position of noise-transfer-function (NTF) zeros, which allows to optimize the modulator's noise shaping. To achieve this, a feedback over two successive first-order MASH stages is added. Two modulator examples are elaborated. Firstly, a 2nd-order MASH architecture consisting of two cascaded first-order stages (a so-called 1–1 structure) is discussed, and it is demonstrated based on computer simulations that the technique functions adequately. Afterwards, a 3rd-order MASH architecture consisting of three cascaded first-order stages (a so-called 1-1-1 structure) is shown. Also here, the approach is found to operate as expected.

A new fully passive noise-shaping architecture for successive approximation register (SAR) analog-to-digital converters (ADCs) was proposed. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. The additional pole increases the efficiency of noise shaping to further 3 dB. So, the use of higher over sampling ratios (OSR) and increased effective number of bits (ENOB) is possible. The architecture was applied to the design of a 9.8-bit ENOB SAR ADC in a 65 nm complementary metal-oxide semiconductor (CMOS) of United Microelectronics Corporation (UMC) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architecture provides 3.8 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s.

Power supply voltage (Vdd) scaling in each era is making difficult to manage speed and power trade-off. Latch is a basic component in wireless and wireline communication to enable data transmission at Gbps. Conventional latches minimise the trade-off at the cost of layout area and average power (Pavg). Coupled to a common power delivery network (PDN) and a CPU core drawing abrupt current, a 2-level latch is presented and evaluated to understand performance under process, voltage, temperature (PVT) and AC noise. An analytical delay model is also derived to understand Pavg- delay (td) trade-off. The delay model gives simple expression suitable for manual evaluation of td. The Pavg, td, power-delay-product (PDP) and figure of merit (FoM) in post-layout are 28.5 μW, 140.4 ps, 4 fJ and 172.3 ns×fJ×µm2, respectively, in 90-nm CMOS and 0.45 V Vdd. Nonetheless, at distinct corner the metrics change by 0.01 μW, 0.2 ps, 0.005 fJ and 0.4 ns×fJ×µm2, respectively, for 1°C shift in temperature. The variations for 1 mV drop in Vdd are 0.2 μW, 1 ps, 0.005 fJ and 1.4 ns×fJ×µm2, respectively. Despite this, the voltage close to the die VP oscillates with time as the CPU pumps current. The td due to AC fluctuating noise, namely, 1st droop, 2nd droop, so forth and DC (various voltage levels) are quite different. The Ldi/dt noise so generated due to the oscillations in VP introduces jitter in the output swing.

This brief presents a ping-pong continuous-time noise-shaping successive-approximation register (CT NS-SAR) analog-to-digital converter (ADC) architecture. Compared with the previous works, two ping-pong operation DACs are utilized to release the conversion time from 5% to 95% of the clock period, while ensuring the continuity of CT integration in the time domain, thus realizing the ideal noise transfer function (NTF) of the true CT-NS SAR. The DAC of each channel performs two roles of integration and conversion alternately, not only converting the signal in the current period but also bringing the generated residue voltage into the next period. Besides, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{ {m}}$</tex-math> </inline-formula>-OTA-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> integrator replaces the open-loop <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{ {m}}$</tex-math> </inline-formula>-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> integrator, where the OTA isolates the output parasitic capacitance, achieving an exact CT integration. The effective conversion bits are calculated by the bandwidth (BW) and the time of bit cycle, thus avoiding the redundant bits. Verified by postsimulation in a 65-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB over 20-MHz BW with an oversampling ratio (OSR) of 15. Under a 1.2-V supply voltage, the ADC consumes 2.3 mW and exhibits a Schreier figure of merit (FoM<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{ {S}}$</tex-math> </inline-formula>) of 170.2 dB.

A low power second order hybrid loopfilter Sigma-Delta modulator with high resolution is presented. The structure is composed by a first active integrator followed by a switched-capacitor (SC) integrator. This modulator architecture exploits the coefficient scaling property of the active integrator, while the SC integrator is modified to shift its pole from inside the unit circle to z=1 at DC in the z-domain. Poles of the loopfilter are zeroes of the noise transfer function (NTF). As a result the NTF zero is also shifted to z=1. This NTF zero compensation for the SC integrator will result in better in-band noise suppression & improved noise shaping. The second order hybrid sigma-delta modulator with a 4-bit quantizer and an oversampling ratio (OSR) of 32 is simulated in simulink. The modulator can achieve 89dB SNDR with a dynamic range of 91dB.