A Band-Pass Noise-Shaping Modulator Using the Error-Feedback Structure on a 10-bit SAR ADC

A 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -order noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is presented with the dual-capacitor merge-and-split (DCMS) switching scheme for low-power sensing applications. The proposed switching scheme features the constant common-mode voltage, so the dynamic offset can be relaxed obviously. Meanwhile, compared to the conventional switching scheme, the proposed switching scheme achieves 99.22% reduction in average switching energy and 50% capacitor area saving due to only using the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cm</inf> reference level. Simulation results illustrate that the NS-SAR ADC consumes 6.19 µW when operating at 1-MS/s. It achieves a Schreier FoM of 168.2 dB with 68.13 dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 8 and 1 V supply in 180 nm CMOS process.

This paper presents a resolution-reconfigurable discrete-time dynamic zoom analog-to-digital converter (ADC) with a 20-kHz bandwidth. It employs a coarse 6-bit successive approximation register (SAR) ADC that dynamically updates the references for the post-stage single-bit second-order delta-sigma modulator to obtain a higher resolution with lower power. The sampling rate of the proposed ADC can be configured to be 1.6, 3.2, 6.4 and 10-MS/s such that four resolution modes, including 12, 14, 16 and 18-bit, can be provided accordingly. Note that pole locations of the noise transfer function (NTF) vary with different OSR's, and noise-shaping effect, together with the power efficiency, can be degraded. To solve this issue, the pole-optimization technique is proposed in this paper. In this way can the pole locations be reconfigured according to the specific OSR. Additionally, the bandwidths of the operational amplifiers are also modulated in different oversampling ratio (OSR) scenarios to further improve the energy efficiency. Fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process, the prototype occupies 1.01 mm2. On condition of an OSR of 250, the proposed ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 102.8 dB, while dissipating 1.3 mW.

A new fully passive noise-shaping architecture for successive approximation register (SAR) analog-to-digital converters (ADCs) was proposed. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. The additional pole increases the efficiency of noise shaping to further 3 dB. So, the use of higher over sampling ratios (OSR) and increased effective number of bits (ENOB) is possible. The architecture was applied to the design of a 9.8-bit ENOB SAR ADC in a 65 nm complementary metal-oxide semiconductor (CMOS) of United Microelectronics Corporation (UMC) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architecture provides 3.8 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s.

This article presents a third-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which exploits a hybrid error control topology to increase the order of the noise-transfer function (NTF). This scheme is a hybrid of two NS stages, namely, a cascaded integrator feed-forward (CIFF) and an error feedback (EF). This EF-CIFF structure contributes a more effective NS capability and enhances the robustness of the high-order NTF. An improved dither-based digital calibration is developed to mitigate the harmonic distortion caused by the capacitor mismatch. Due to the usage of an averaging filter, this calibration greatly reduces the interference of quantization noise on mismatch extraction while only needing a minimum modification in a standard SAR Topology. Hence, our scheme is simple and inherently robust to the process, voltage, and temperature variation. Based on an 8-bit SAR, our prototype is fabricated in a 130-nm CMOS process. It consumes a 96- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power when operating at a 2-MS/s sampling frequency with a 1.2-V supply. The proposed NS-SAR yields a peak Schreier figure of merit of 170.7 dB with a signal-to-noise-and-distortion ratio (SNDR) of 79.57 dB at an oversampling ratio of 8.

A successive approximation register (SAR) analog-to-digital converter (ADC) design in 0.18-um CMOS process is presented for wireless power transfer applications. By applying body effect reduction T/H circuit that improved ENOB of the ADC. This proposed ADC uses asynchronous control logic without off-chip frequency clock. The measured consumption of 1.53 mW at input voltage of 1.8 V, sampling rate of 40 MS/s, the proposed design realizes a spurious-free dynamic range (SFDR) of 62.16 dB, an effective number of bits (ENOB) of 8.93 bits, a signal-to-noise and distortion ratio (SNDR) of 55.52 dB, integral nonlinearity (INL) of 1.12 LSB and differential nonlinearity (DNL) of 0.63 LSB. The proposed SAR ADC is build-in internet of thing (IoT) system to meet low power requirement for wireless power receiver applications.

This article presents an energy-efficient high-resolution dual-residue (D-R) pipelined-successive approximation register (SAR) analog-to-digital converter (ADC), with a backend capacitive interpolating SAR ADC incorporated with noise-shaping (NS) capability. The residue amplifier design could be simplified as the residue is pre-amplified by the amplifier for the kT/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C$</tex-math> </inline-formula> -noise cancellation. Moreover, the proposed segmented digital-to-analog converter (DAC) structure overcomes parasitic capacitance limitations in the capacitive interpolation, improving resolution along with the gain-error-free advantage of the D-R structure. Fabricated in a 180-nm CMOS technology, the prototype ADC achieves an 81.2-dB signal-to-noise and distortion ratio (SNDR) and an 89.9-dB spurious-free dynamic range (SFDR) in a 1.5-MHz bandwidth (BW) at an over-sampling ratio (OSR) of 8 with a 170.4-dB SNDR Schreier figure-of-merit (FoM) without any calibration.

Sensor interfaces demand ever-increasing energy efficiency from analog-to-digital converters (ADCs). For sensors requiring a wide dynamic range (DR) (>12 bit), the incremental ADC (IADC) is becoming a popular choice. In this article, the design of an energy-efficient IADC with a 16-bit signal-to-noise and distortion ratio (SNDR) and 17-bit DR is described. The IADC implements a novel capacitor scaling technique, which reduces power consumption in the critical first operational transconductance amplifier (OTA) by up to 37%. The new technique can be combined with the extended counting (EC) scheme utilizing an in-loop 4-bit asynchronous successive approximation register (SAR) (ASAR) ADC. Using a three-phase operation, this IADC architecture further reduces the power while enabling wider signal bandwidth with a much lower oversampling ratio (OSR). Silicon measurements in a 0.18- $\mu $ m CMOS process show the IADC achieved a DR of 102.2 dB, within a bandwidth of 2.04 kHz, with power consumption of about $25~\mu $ W, leading to a state-of-the-art Schreier figure-of-merit (FoM) of 181.1 dB.

This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the voltage-to-time converter (VTC) and TDC realize an inherent process, voltage, and temperature (PVT) robustness by inner tracking, thus inducing no extra power and circuit overheads. The voltage-domain and time-domain speed-enhanced techniques accelerate the first- and second-stage ADC conversions under a low power supply, respectively. Furthermore, in cooperation with a detect-and-skip switching scheme in the SAR ADC and an offset bit-shifting scheme in the two-step TDC, the ADC achieves linearity of 13 bit. The prototype ADC was fabricated in a 65-nm CMOS process with a 0.6-V power supply, achieving a 71.0-dB signal-to-noise and distortion ratio (SNDR) and an 89.5-dB spurious-free dynamic range with a Nyquist input at 20 MS/s, while exhibiting a Schreier figure-of-merit (FoM) of 181.9 dB. The ADC presents a sub-1-dB SNDR drop across a temperature range of −50 to 90 °C and ±5% power-supply variation.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

This brief presents a ping-pong continuous-time noise-shaping successive-approximation register (CT NS-SAR) analog-to-digital converter (ADC) architecture. Compared with the previous works, two ping-pong operation DACs are utilized to release the conversion time from 5% to 95% of the clock period, while ensuring the continuity of CT integration in the time domain, thus realizing the ideal noise transfer function (NTF) of the true CT-NS SAR. The DAC of each channel performs two roles of integration and conversion alternately, not only converting the signal in the current period but also bringing the generated residue voltage into the next period. Besides, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{ {m}}$</tex-math> </inline-formula>-OTA-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> integrator replaces the open-loop <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{ {m}}$</tex-math> </inline-formula>-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> integrator, where the OTA isolates the output parasitic capacitance, achieving an exact CT integration. The effective conversion bits are calculated by the bandwidth (BW) and the time of bit cycle, thus avoiding the redundant bits. Verified by postsimulation in a 65-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB over 20-MHz BW with an oversampling ratio (OSR) of 15. Under a 1.2-V supply voltage, the ADC consumes 2.3 mW and exhibits a Schreier figure of merit (FoM<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{ {S}}$</tex-math> </inline-formula>) of 170.2 dB.

The performance of a sigma-delta analog-to-digital converter (ADC) critically depends on one or more of the main three parameters: over-sampling ratio, the order of the modulators, and the number of bits used. Increasing each one of these parameters presents a degree of challenge (i.e., the increase in the over-sampling ratio is limited by the technology and the power consumption requirement). This paper presents a method to obtain high order noise shaping with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -path architectures that are based on first-order or second-order modulators. The desired noise transfer function (NTF) is obtained by suitable cross-coupling paths. The method was applied to a two-path first-order modulator for obtaining a second-order noise shaping. The performances of the proposed sigma-delta ADC were verified at the behavioral and transistor level implemented in 90-nm CMOS technology.

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

This paper presents the design of a low-power high-dynamic-range analog-to-digital converter (ADC) for solid-state radiation detectors, in particular Cadmium Zinc Telluride (CZT). The core of the ADC consists of a Wilkinson-type digitizer, a digital control unit and a 9-bit counter. The analog core of the ADC operates from a 3.3 V supply while the supply for the digital control circuitry is 1.2 V. The input dynamic range of the ADC is 2.7 V and the ADC consumes 631 μW. The ADC is designed and laid-out in a standard 0.13-μm CMOS process and occupies 0.026 mm2. Post-layout simulation results show that the signal-to-noise and distortion ratio (SNDR) of the ADC is just over 50 dB which corresponds to an effective number of bits (ENOB) of approximately 8. The simulated differential and integral nonlinearities (DNL and INL) are ±0.065 LSB and 0.954 LSB, respectively.

This paper presents a new single channel 6-bit 900MS/s asynchronous binary search analog to digital converter (ADC). The proposed ADC works based on binary search principle like the Successive Approximation Register (SAR) ADC. Compared to SAR ADC the speed is improved significantly adopting two design techniques. By implementing the binary search in an open loop configuration using asynchronous clock generation the delay in the feedback path of the SAR ADC is relaxed significantly. Moreover in the proposed asynchronous binary search ADC two bits are resolved in each stage of the ADC. By resolving two bits in each stage the proposed ADC can operate twice as fast as conventional asynchronous binary search ADCs. The proposed single channel 6-bit 900MS/s ADC was designed in 90nm CMOS process. Simulation results show that the proposed ADC reaches a peak SNDR of 35.82dB consuming 4.33mW from a single 1.2V power supply. It achieves of 95.3fJ/conv.code FoM.

This paper introduces a wirelessly powered scattered neural recording wearable system that can facilitate continuous, untethered, and long-term electroencephalogram (EEG) recording. The proposed system, including 32 standalone EEG recording devices and a central controller, is incorporated in a wearable form factor. The standalone devices are sparsely distributed on the scalp, allowing for flexible placement and varying quantities to provide extensive spatial coverage and scalability. Each standalone device featuring a low-power EEG recording application-specific integrated circuit (ASIC) wirelessly receives power through a 60 MHz inductive link. The low-power ASIC design (84.6 µW) ensures sufficient wireless power reception through a small receiver (Rx) coil. The 60 MHz inductive link also serves as the data carrier for wireless communication between standalone devices and the central controller, eliminating the need for additional data antennas. All these efforts contribute to the miniaturization of standalone devices with dimensions of 12 × 12 × 5 mm3, enhancing device wearability. The central controller applies the pulse width modulation (PWM) scheme on the 60 MHz carrier, transmitting user commands at 4 Mbps to EEG recording ASICs. The ASIC employs a novel synchronized PWM demodulator to extract user commands, operating signal digitization and data transmission. The analog frontend (AFE) amplifies the EEG signal with a gain of 45 dB and applies band-pass filtering from 0.03 Hz to 400 Hz, with an input-referred noise (IRN) of 3.62 µVRMS. The amplified EEG signal is then digitized by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with a peak signal-to-noise and distortion ratio (SNDR) of 55.4 dB. The resulting EEG data is transmitted to an external software-defined radio (SDR) Rx through load-shift-keying (LSK) backscatter at 3.75 Mbps. The system's functionality is fully evaluated in human experiments.