A Reconfigurable 12-to-18-Bit Dynamic Zoom ADC With Pole-Optimized Technique

A new fully passive noise-shaping architecture for successive approximation register (SAR) analog-to-digital converters (ADCs) was proposed. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. The additional pole increases the efficiency of noise shaping to further 3 dB. So, the use of higher over sampling ratios (OSR) and increased effective number of bits (ENOB) is possible. The architecture was applied to the design of a 9.8-bit ENOB SAR ADC in a 65 nm complementary metal-oxide semiconductor (CMOS) of United Microelectronics Corporation (UMC) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architecture provides 3.8 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s.

This paper presents a band-pass noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) with a second-order modulator which is comprised of a fully passive switched-capacitor (SC) filter and a gain-boosted dynamic amplifier. It employs the error-feedback (EF) structure in a simple method to implement the complicated noise transfer function (NTF) zeros, which enhances the noise-shaping capability by minimally modifying a standard SAR ADC. Designed in 28 nm CMOS process, the prototype of proposed NS-SAR ADC achieves 76.84 dB signal-to-noise and distortion ratio (SNDR) with the bandwidth between 20 and 40 MHz and the FoMw is only 2.24 fJ/step at the oversampling ratio (OSR) of 5.

Energy consumption is very critical for environmental monitoring using wireless sensor networks, thus, every block must be designed to consume low energy to be within the limited energy budget of a sensor node. In the context of improving the power efficiency of the analog-to-digital converter (ADC), for this specific application, successive approximation register (SAR) ADC is the best architecture to use. In addition, coarse-fine technique has been proven to reduce power consumption in SAR ADCs. However, design considerations involving the coarse ADC bit allocation are important but not discussed in literature. These includes the following: trade off between resolution of the coarse stage and the accuracy of the ADC; trade off between the energy consumption, accuracy and speed of the comparator block; and trade off between energy consumption and accuracy of different switching schemes for the digital-to-analog (DAC) block. This project produced models of these trade-offs, provided a methodology in designing coarse-fine SAR ADCs, implemented two ADCs in the schematic level: the one with the lowest energy consumption; and the one with the highest Schreier figure of merit (FoMs), and implemented the ADC with the lowest energy consumption in the layout level. Optimization using the MATLAB model in the DAC lead to k = 4 which gives the lowest power and k = 3 which gives the highest Schreier FoM. Schematic implementation at 50kSps of k = 4 and k = 3 gave: 2.201pJ and 2.3617pJ switching energy; 9.2 and 9.3 ENOB; and 170.96 dB and 170.72 dB Schreier FoM, respectively. This project was also able to match the trends of the models to the simulations although there are deviations of values. However, ENOBs fall within the target range of ENOBs.

This paper presents a new single channel 6-bit 900MS/s asynchronous binary search analog to digital converter (ADC). The proposed ADC works based on binary search principle like the Successive Approximation Register (SAR) ADC. Compared to SAR ADC the speed is improved significantly adopting two design techniques. By implementing the binary search in an open loop configuration using asynchronous clock generation the delay in the feedback path of the SAR ADC is relaxed significantly. Moreover in the proposed asynchronous binary search ADC two bits are resolved in each stage of the ADC. By resolving two bits in each stage the proposed ADC can operate twice as fast as conventional asynchronous binary search ADCs. The proposed single channel 6-bit 900MS/s ADC was designed in 90nm CMOS process. Simulation results show that the proposed ADC reaches a peak SNDR of 35.82dB consuming 4.33mW from a single 1.2V power supply. It achieves of 95.3fJ/conv.code FoM.

A successive approximation register (SAR) analog-to-digital converter (ADC) design in 0.18-um CMOS process is presented for wireless power transfer applications. By applying body effect reduction T/H circuit that improved ENOB of the ADC. This proposed ADC uses asynchronous control logic without off-chip frequency clock. The measured consumption of 1.53 mW at input voltage of 1.8 V, sampling rate of 40 MS/s, the proposed design realizes a spurious-free dynamic range (SFDR) of 62.16 dB, an effective number of bits (ENOB) of 8.93 bits, a signal-to-noise and distortion ratio (SNDR) of 55.52 dB, integral nonlinearity (INL) of 1.12 LSB and differential nonlinearity (DNL) of 0.63 LSB. The proposed SAR ADC is build-in internet of thing (IoT) system to meet low power requirement for wireless power receiver applications.

A 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -order noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is presented with the dual-capacitor merge-and-split (DCMS) switching scheme for low-power sensing applications. The proposed switching scheme features the constant common-mode voltage, so the dynamic offset can be relaxed obviously. Meanwhile, compared to the conventional switching scheme, the proposed switching scheme achieves 99.22% reduction in average switching energy and 50% capacitor area saving due to only using the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cm</inf> reference level. Simulation results illustrate that the NS-SAR ADC consumes 6.19 µW when operating at 1-MS/s. It achieves a Schreier FoM of 168.2 dB with 68.13 dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 8 and 1 V supply in 180 nm CMOS process.

We propose a hybrid Analog to Digital Converter (ADC) combined with the first-stage as a first-order feedforward incremental (FF I-) ADC and the second-stage as a SAR (Successive Approximation Register) ADC as high-precision and high-speed ADCs. As a result of simulation, the proposed hybrid ADC correctly converts data even if capacitance in FF path of the first-order I-ADC has 10% error.

A resolution-independent successive approximation register (SAR) analog to digital converter (ADC) architecture based on a switched capacitor integrator is presented. Digital to analog converter (DAC) architecture uses charge sharing and integration principle for reference generation, using only six unit capacitors for a fully differential version. A 10-bit, 1.8-V and 0.9-MS/s SAR ADC is designed in 180-nm CMOS process. ADC architecture is area efficient when compared with SAR ADC with a binary weighted capacitor array DAC. The architecture is largely parasitic insensitive, also programmable resolution is possible with no hardware overhead.

In recent years, we have come across a growing need for the design of low power, long battery life Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC). ADCs are the major component of all the systems which need to process an analogue signal obtained from measuring real world parameters and hence they need to be efficient enough depending on the application and power constraint of the device. Speed is also an important parameter as it is used in many real time applications. The basic components of the SAR ADC can be implemented using circuits of various logics available for the logic gates, adders, comparators utilised in it. This paper presents the working of 4-bit successive approximation register analog-to-digital converters (SAR ADC) in three different logics namely, Complementary Metal Oxide Semiconductors (CMOS), Transmission Gates (TG), and Double Pass Transistors (DPL) logics, which were used in the basic components of each major block of the ADC. The aim of this paper here is to compare the various parameters such as area, power consumption and delay between the three different technologies chosen above. The SAR ADCs were implemented for this purpose in 90nm Technology using the Cadence Virtuoso Design Tool building schematics and layouts for the same and calculating the various parameters required for the above-mentioned comparison.

In this paper, we study on the automatic gain control (AGC) scheme for pulse amplitude modulation (PAM) with 1.8-V 10-bit 100MS/s successive approximation register (SAR) analog-to-digital converter (ADC) analog-to-digital converters (ADCs) by TSMC 0.18-um CMOS process. For M-PAM networked control systems, this design investigate the problem of AGC schemes under the assumption that applied ten comparators followed by an asynchronous trigger logic, the proposed SAR ADC achieves high speed operation are used at the receiver end. Compared to the conventional SAR ADC, there is no significant delay in the digital feedback logic on robotic wireless control system. With the sampling rate limited only by the ten delays of the capacitor DAC settling and comparators quantization. For of the fixed threshold ADCs, and altering the gain to ADC input, we propose an algorithm based on ADC output's distribution-function to adjust the gain of the amplifier in front of the ADC.

This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the voltage-to-time converter (VTC) and TDC realize an inherent process, voltage, and temperature (PVT) robustness by inner tracking, thus inducing no extra power and circuit overheads. The voltage-domain and time-domain speed-enhanced techniques accelerate the first- and second-stage ADC conversions under a low power supply, respectively. Furthermore, in cooperation with a detect-and-skip switching scheme in the SAR ADC and an offset bit-shifting scheme in the two-step TDC, the ADC achieves linearity of 13 bit. The prototype ADC was fabricated in a 65-nm CMOS process with a 0.6-V power supply, achieving a 71.0-dB signal-to-noise and distortion ratio (SNDR) and an 89.5-dB spurious-free dynamic range with a Nyquist input at 20 MS/s, while exhibiting a Schreier figure-of-merit (FoM) of 181.9 dB. The ADC presents a sub-1-dB SNDR drop across a temperature range of −50 to 90 °C and ±5% power-supply variation.

Fluorescence biophotometry measurements require wide dynamic range (DR) and high sensitivity laboratory apparatus. Indeed, it is often very challenging to accurately resolve the small fluorescence variations in presence of high background tissue autofluorescence. There is a great need for smaller detectors combining high linearity, high sensitivity, and high-energy efficiency. This paper presents a new high-dynamic range CMOS photodetector embedding a photosensor and a high-precision two-step analog-to-digital converter (ADC) with a noise cancellation scheme. In this system, a 16-bit two-step ADC sucessivley uses an integrating ADC and a successive approximation register (SAR) ADC enabling wide dynamic range and high energy-efficiency photocurrent quantization. Noise cancellation is achieved through a SAR digital-to-analog (DAC) capacitor bank to store and subtract the low-frequency noise from the output of a capacitive transimpedance amplifier (CTIA) throughout each data conversion. The 6-most significant bits are resolved through the integrating ADC, while the 10-least significant bits are extracted by the SAR ADC. The two-step data converter uses a hardware sharing scheme to decrease the chip size and to improve energy-efficiency. The proposed optoelectronic detector is implemented in a 0.18-µm CMOS technology, consuming 60 µW from a 3.3-V supply voltage while achieving a DR of 94 dB, a minimum detectable current of 200-ƒA rms , at 1-kS/s sampling rate. The proposed biosensor presents a FOM of 1.46 pJ/conv. which is among the best reported performance among similar systems.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

This brief presents a ping-pong continuous-time noise-shaping successive-approximation register (CT NS-SAR) analog-to-digital converter (ADC) architecture. Compared with the previous works, two ping-pong operation DACs are utilized to release the conversion time from 5% to 95% of the clock period, while ensuring the continuity of CT integration in the time domain, thus realizing the ideal noise transfer function (NTF) of the true CT-NS SAR. The DAC of each channel performs two roles of integration and conversion alternately, not only converting the signal in the current period but also bringing the generated residue voltage into the next period. Besides, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{ {m}}$</tex-math> </inline-formula>-OTA-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> integrator replaces the open-loop <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{ {m}}$</tex-math> </inline-formula>-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> integrator, where the OTA isolates the output parasitic capacitance, achieving an exact CT integration. The effective conversion bits are calculated by the bandwidth (BW) and the time of bit cycle, thus avoiding the redundant bits. Verified by postsimulation in a 65-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB over 20-MHz BW with an oversampling ratio (OSR) of 15. Under a 1.2-V supply voltage, the ADC consumes 2.3 mW and exhibits a Schreier figure of merit (FoM<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{ {S}}$</tex-math> </inline-formula>) of 170.2 dB.

This article presents a 9-bit 500-MS/s 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with an error-tolerant interpolation technique. The proposed interpolation technique uses flip-flops to implement a 2-bit/cycle operation in the SAR ADC. By taking advantage of the metastable region of the flip-flop, the proposed interpolator can defer the bit decision when a decision error occurs with a high probability. Because the SAR ADC approximates the signal range step by step, the deferred decisions proceed to the next conversion cycles without any increase in quantization noise. The deferring-decision characteristic increases the error tolerance in the presence of comparator mismatches and increases the inherent linearity of the interpolation technique compared to conventional latch interpolation. A prototype ADC was designed using the 28-nm CMOS technology to verify the effectiveness of the proposed interpolation technique. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) at the Nyquist rate are 50.6 and 61.4 dB, respectively. The power consumption is 1.87 mW at a sampling frequency of 500 MS/s. The proposed ADC achieves a Walden figure of merit (FoM) of 13.5 fJ/conversion-step.